ATA5773-DK1 Atmel, ATA5773-DK1 Datasheet - Page 93

• Manufacturer Part Number: ATA5773-DK1
• Description: BOARD XMITTER FOR ATA5773 315MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5773-DK1

• Frequency: 315MHz
• Maximum Frequency: 315 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 9 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5773
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.15.9.6
4.15.9.7
9137E–RKE–12/10
TIMSK0 – Timer/Counter 0 Interrupt Mask Register
TIFR0 – Timer/Counter 0 Interrupt Flag Register
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny44V and will always read as zero.
• Bit 2– OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR0.
• Bit 1– OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is exe-
cuted if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0– TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny44V and will always read as zero.
• Bit 2– OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data
in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one
to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt
Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1– OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the
data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt
Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
Bit
0x39 (0x59)
Read/Write
Initial Value
Bit
0x38 (0x58)
Read/Write
Initial Value
R
7
–
0
R
7
–
0
R
6
–
0
R
6
–
0
R
5
–
0
R
5
–
0
R
4
–
0
4
–
R
0
R
3
–
0
R
3
–
0
Atmel ATA5771/73/74
OCIE0B
OCF0B
R/W
R/W
2
0
2
0
OCIE0A
OCF0A
R/W
R/W
1
0
1
0
TOIE0
TOV0
R/W
R/W
0
0
0
0
TIMSK0
TIFR0
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