ATA5773-DK1 Atmel, ATA5773-DK1 Datasheet - Page 157

• Manufacturer Part Number: ATA5773-DK1
• Description: BOARD XMITTER FOR ATA5773 315MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5773-DK1

• Frequency: 315MHz
• Maximum Frequency: 315 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 9 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5773
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.20.10.4
9137E–RKE–12/10
ADCSRB – ADC Control and Status Register B
• Bits 7 – BIN: Bipolar Input Mode
The gain stage is working in the unipolar mode as default, but the bipolar mode can be
selected by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided
conversions are supported and the voltage on the positive input must always be larger than
the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In
the bipolar mode two-sided conversions are supported and the result is represented in the
two’s complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the
resolution is 9 bits + 1 sign bit.
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
See
• Bit 5 – Res: Reserved Bit
This bit is reserved bit in the Atmel
• Bit 4 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Regis-
ter. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted.
Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any
ongoing conversions. For a comple the description of this bit, see
and ADCH – ADC Data Register” on page
• Bit 3 – Res: Reserved Bit
This bit is reserved bit in the ATtiny44V and will always read as what was wrote there.
• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from
a trigger source that is cleared to a trigger source that is set, will generate a positive edge on
the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free
Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is
set
Bit
0x03 (0x23)
Read/Write
Initial Value
.
Section 4.20.10.4 “ADCSRB – ADC Control and Status Register B” on page
R/W
BIN
7
0
ACME
R/W
6
0
R/W
®
5
–
0
ATtiny44V and will always read as what was wrote there.
ADLAR
R/W
156.
4
0
R/W
3
–
0
Atmel ATA5771/73/74
ADTS2
R/W
2
0
ADTS1
Section 4.20.10.3 “ADCL
R/W
1
0
ADTS0
R/W
0
0
157.
ADCSRB
157