ATA5773-DK1 Atmel, ATA5773-DK1 Datasheet - Page 101

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ATA5773-DK1

Manufacturer Part Number
ATA5773-DK1
Description
BOARD XMITTER FOR ATA5773 315MHZ
Manufacturer
Atmel
Type
Transmitterr
Datasheets

Specifications of ATA5773-DK1

Frequency
315MHz
Maximum Frequency
315 MHz
Supply Voltage (max)
4 V
Supply Voltage (min)
2 V
Supply Current
9 mA
Product
RF Development Tools
For Use With/related Products
ATA5773
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
4.16.6
9137E–RKE–12/10
Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and
give them a time-stamp indicating time of occurrence. The external signal indicating an event,
or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator
unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features
of the signal applied. Alternatively the time-stamps can be used for creating a log of the
events.
The Input Capture unit is illustrated by the block diagram shown in
of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The
small “n” in register and bit names indicates the Timer/Counter number.
Figure 4-39. Input Capture Unit Block Diagram
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alterna-
tively on the Analog Comparator output (ACO), and this change confirms to the setting of the
edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the
counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag
(ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If
enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1
flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 flag can be
cleared by software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low
byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is cop-
ied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location
it will access the TEMP Register.
ICPn
WRITE
ICRnH (8-bit)
TEMP (8-bit)
Comparator
Analog
ICRn (16-bit Register)
ACO*
ICRnL (8-bit)
ACIC*
DATA BUS
Canceler
ICNC
Noise
(8-bit)
Atmel ATA5771/73/74
TCNTnH (8-bit)
TCNTn (16-bit Counter)
Detector
ICES
Edge
Figure
TCNTnL (8-bit)
4-39. The elements
ICFn (Int.Req.)
101

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