ATA5773-DK1 Atmel, ATA5773-DK1 Datasheet - Page 59

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ATA5773-DK1

Manufacturer Part Number
ATA5773-DK1
Description
BOARD XMITTER FOR ATA5773 315MHZ
Manufacturer
Atmel
Type
Transmitterr
Datasheets

Specifications of ATA5773-DK1

Frequency
315MHz
Maximum Frequency
315 MHz
Supply Voltage (max)
4 V
Supply Voltage (min)
2 V
Supply Current
9 mA
Product
RF Development Tools
For Use With/related Products
ATA5773
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
4.13.2.3
4.13.2.4
9137E–RKE–12/10
GIFR – General Interrupt Flag Register
PCMSK1 – Pin Change Mask Register 1
• Bit 4– PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
• Bits 7, 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny44V and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes
set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 5 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT11..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 4– PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 7, 4– Res: Reserved Bits
These bits are reserved bits in the ATtiny44V and will always read as zero.
• Bits 3..0 – PCINT11..8: Pin Change Enable Mask 11..8
Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT11..8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT11..8 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit
0x3A (0x5A)
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
R
7
0
R
7
0
INTF0
R
6
0
R/W
6
0
R
PCIF1
5
0
R/W
5
0
R
4
0
PCIF0
R/W
4
0
PCINT11
R/W
3
0
Atmel ATA5771/73/74
R
3
0
PCINT10
R/W
2
0
R
2
0
PCINT9
R/W
1
0
R
1
0
PCINT8
R/W
0
0
0
R
0
PCMSK1
GIFR
59

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