ATA5773-DK1 Atmel, ATA5773-DK1 Datasheet - Page 123

• Manufacturer Part Number: ATA5773-DK1
• Description: BOARD XMITTER FOR ATA5773 315MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5773-DK1

• Frequency: 315MHz
• Maximum Frequency: 315 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 9 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5773
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.17
4.17.1
4.17.1.1
9137E–RKE–12/10
Timer/Counter Prescaler
Prescaler Reset
External Clock Source
Timer/Counter 0, and 1 share the same prescaler module, but the Timer/Counters can have
different prescaler settings. The description below applies to all Timer/Counters. Tn is used as
a general name, n = 0, 1.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
used as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/CounterCounter, and it is shared by the Timer/Counter Tn. Since the prescaler is not
affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs
when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of sys-
tem clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1
system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The syn-
chronized (sampled) signal is then passed through the edge detector.
functional equivalent block diagram of the Tn synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (
transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 4-50. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock
cycles from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is
generated.
CLK_I/O
Tn
/256, or f
clk
I/O
CLK_I/O
D
LE
Q
/1024.
Synchronization
CLK_I/O
D
Q
). Alternatively, one of four taps from the prescaler can be
T
0
pulse for each positive (CSn2:0 = 7) or negative
Atmel ATA5771/73/74
D
Q
Edge Detector
Figure 4-50
CLK_I/O
clk
I/O
). The latch is
/8, f
Tn_sync
(To Clock
Select Logic)
CLK_I/O
shows a
Tn
). The
/64,
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