ATA5773-DK1 Atmel, ATA5773-DK1 Datasheet - Page 170

• Manufacturer Part Number: ATA5773-DK1
• Description: BOARD XMITTER FOR ATA5773 315MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5773-DK1

• Frequency: 315MHz
• Maximum Frequency: 315 MHz
• Supply Voltage (max): 4 V
• Supply Voltage (min): 2 V
• Supply Current: 9 mA
• Product: RF Development Tools
• For Use With/related Products: ATA5773
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.23.6.1
170
Atmel ATA5771/73/74
Serial Programming Algorithm
When programming the EEPROM, an auto-erase cycle is built into the self-timed program-
ming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the Atmel
When reading data from the ATtiny44V, data is clocked on the falling edge of SCK. See
8-3 on page 193
To program and verify the ATtiny44V in the Serial Programming mode, the following sequence
is recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte
must be loaded before data high byte is applied for a given address. The Program
memory Page is stored by loading the Write Program memory Page instruction with the
3 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least
t
serial programming interface before the Flash write operation completes can result in
incorrect programming.
WD_FLASH
before issuing the next page. (See
and
Figure 8-4 on page 193
CC
and GND while RESET and SCK are set to “0”. In some sys-
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
®
ATtiny44V, data is clocked on the rising edge of SCK.
for timing details.
Table 4-65 on page
Table 4-66 on page
ck
ck
171.) Accessing the
>= 12MHz
>= 12MHz
172):
9137E–RKE–12/10
Figure