SAK-TC1796-256F150E BC Infineon Technologies, SAK-TC1796-256F150E BC Datasheet - Page 75

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SAK-TC1796-256F150E BC

Manufacturer Part Number
SAK-TC1796-256F150E BC
Description
IC MCU 32BIT FLASH BGA-416
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet

Specifications of SAK-TC1796-256F150E BC

Core Processor
TriCore
Core Size
32-Bit
Speed
150MHz
Connectivity
ASC, CAN, EBI/EMI, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
123
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 44x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
416-BGA
Data Bus Width
32 bit
Data Ram Size
256 KB
Interface Type
2xASC, 2xSSC, 2xMSC, 2xMLI
Maximum Clock Frequency
150 MHz
Number Of Programmable I/os
123
Number Of Timers
260
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 10 bit, 12 bit, 44 Channel
Packages
P-BGA-416
Max Clock Frequency
150.0 MHz
Sram (incl. Cache)
256.0 KByte
Can Nodes
4
A / D Input Lines (incl. Fadc)
44
Program Memory
2.0 MB
For Use With
B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
SAKTC1796256F150EBCT
SP000097527
SP000097528
OCDS Level 1 Debug Support
The OCDS Level 1 debug support is mainly assigned for real-time software debugging
purposes which have a demand for low-cost standard debugger hardware.
The OCDS Level 1 debug support is based on a JTAG interface which can be used by
the external debug hardware to communicate with the system. The on-chip Cerberus
module controls the interactions between the JTAG interface and the on-chip modules.
The external debug hardware may become master of the internal buses and read or
write the on-chip register/memory resources. The Cerberus also allows to define
breakpoint and trigger conditions as well as to control user program execution (run/stop,
break, single-step).
OCDS Level 2 Debug Support
The OCDS Level 2 debug support allows to implement program tracing capabilities for
enhanced debuggers by extending the OCDS Level 1 debug functionality with an
additional 16-bit wide trace port with trace clock. With the trace extension the following
four trace capabilities are provided (only one of the four trace capabilities can be
selected at a time):
OCDS Level 3 Debug Support
The OCDS Level 3 debug support is based on a special emulation device, the
TC1796ED, which provides additional features required for high-end emulation
purposes. The TC1796ED is a device which includes the TC1796 product chip and
additional emulation extension hardware in a package with the same footprint as the
TC1796.
Data Sheet
Trace capability of the CPU program flow
Trace capability of the PCP2 program flow
Trace capability of the DMA Controller transaction requests
Trace capability of the DMA Controller move engine status information
75
Functional Description
V1.0, 2008-04
TC1796

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