SAK-TC1796-256F150E BC Infineon Technologies, SAK-TC1796-256F150E BC Datasheet - Page 107

• Manufacturer Part Number: SAK-TC1796-256F150E BC
• Description: IC MCU 32BIT FLASH BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: 2xASC, 2xSSC, 2xMSC, 2xMLI
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 123
• Number Of Timers: 260
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 10 bit, 12 bit, 44 Channel
• Packages: P-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No
• Other names: SAKTC1796256F150EBCT; SP000097527; SP000097528

2) Parameter test correlation for
4.3.3
There is a restriction for the power sequencing of the 3.3 V domain including
shown in
shows the valid range for
V
referenced in
anti parallel ESD protection diodes in TC1796 design steps BC and BD. The
V
diodes in TC1796 design step BE.
V
V
Figure 29
All ground pins
The difference voltage between the ground pins must not exceed 200 mV.
The PORST signal must be activated at latest before any power supply voltage falls
below the levels shown on the figure below. In this case, only the memory row of a Flash
memory that was a target of a write at the moment of the power loss will contain
unreliable content. Additionally, the PORST signal should be activated as soon as
possible. The sooner the PORST signal is activated, the less time the system operates
outside of the normal operating power supply range.
Data Sheet
DDP
DDMF
DD
DDEBU
,
,
V
,
V
DDOSC
belongs to its own 2.5V to 3.3V domain.
V
DDOSC3
DDP
Figure
Power Sequencing
,
and
(3.3V)
Figure 29
V
,
V
V
3.3V
1.5V
V
V
DDOSC3
DDP
DDP
SS
29: it must always be higher than 1.5 V domain - 0.5 V. The grey area
DDFL3
V
DDAF
/
must be externally connected to one single star point in the system.
V
,
DDEBU
PORST
sub domains are connected with anti parallel ESD protection
belong to the 1.5 V power supply domain, referenced as
V
as
DDM
V
V
DDEBU
3.3V
V
,
/
3.3
V
V
and
. The
DDMF
DD
= 2.5 V ± 5%
V
3.3
Power Up Sequence
V
, V
belong to the 3.3 V power supply domain, that is
DDEBU
V
DDEBU
DDM
107
> V
relative to an exemplary 1.5 V ramp.
and
1.5
- 0.5V
V
DDMF
sub domains are connected with
V
V
1.5
3.3
, V
Electrical Parameters
DDEBU
PowerSeq 2
Time
Time
V1.0, 2008-04
V
TC1796
DDEBU
V
V
1.5
DDM
.
as
,