SAK-TC1796-256F150E BC Infineon Technologies, SAK-TC1796-256F150E BC Datasheet - Page 17

• Manufacturer Part Number: SAK-TC1796-256F150E BC
• Description: IC MCU 32BIT FLASH BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: 2xASC, 2xSSC, 2xMSC, 2xMLI
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 123
• Number Of Timers: 260
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 10 bit, 12 bit, 44 Channel
• Packages: P-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No
• Other names: SAKTC1796256F150EBCT; SP000097527; SP000097528

Table 2
Symbol
Parallel Ports
P0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
Data Sheet
Pins
A9
A8
A7
B8
B7
A6
B6
C8
C7
B5
C6
D6
C5
D5
A5
D4
Pin Definitions and Functions (cont’d)
I/O Pad
I/O A1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Class
Power
Supply
V
DDP
17
Functions
Port 0
Port 0 is a 16-bit bidirectional general-
purpose I/O port.
Port 0 I/O line 0
Port 0 I/O line 1
Port 0 I/O line 2
Port 0 I/O line 3
Port 0 I/O line 4
Port 0 I/O line 5
Port 0 I/O line 6
Port 0 I/O line 7
Port 0 I/O line 8
Port 0 I/O line 9
Port 0 I/O line 10
Port 0 I/O line 11
Port 0 I/O line 12
Port 0 I/O line 13
Port 0 I/O line 14
Port 0 I/O line 15
The states of the Port 0 pins are latched into
the software configuration input register
SCU_SCILR at the rising edge of HDRST.
Therefore, Port 0 pins can be used for
operating mode selections by software.
General Device Information
V1.0, 2008-04
TC1796