SAK-TC1796-256F150E BC Infineon Technologies, SAK-TC1796-256F150E BC Datasheet - Page 65

• Manufacturer Part Number: SAK-TC1796-256F150E BC
• Description: IC MCU 32BIT FLASH BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: 2xASC, 2xSSC, 2xMSC, 2xMLI
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 123
• Number Of Timers: 260
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 10 bit, 12 bit, 44 Channel
• Packages: P-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No
• Other names: SAKTC1796256F150EBCT; SP000097527; SP000097528

3.16
The FADC module of the TC1796 basically is a 4-channel A/D converter with 10-bit
resolution that operates by the method of the successive approximation.
The main FADC functional blocks shown in
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The FADC module is supplied by the following power supply and reference voltage lines:
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Data Sheet
The Input Stage contains the differential inputs and the programmable amplifier.
The A/D Converter is responsible for the analog-to-digital conversion.
The Data Reduction Unit contains programmable anti aliasing and data reduction
filters.
The Channel Trigger Control block defines the trigger and gating conditions for the
four FADC channels. The gating source inputs GS[7:0] and trigger source inputs
TS[7:0] are connected with GPTA0 module outputs, with GPIO port lines, and
external request unit outputs.
The Channel Timers can independently trigger the conversion of each FADC
channel.
The A/D control block is responsible for the overall FADC functionality.
V
V
V
DDMF
DDAF
FAREF
/
/
V
/
V
V
DDAF
Fast Analog-to-Digital Converter Unit (FADC)
DDMF
FAGND
:
:
: FADC Reference Voltage/FADC Reference Ground
FADC Analog Part Power Supply (3.3V)
FADC Analog Part Logic Power Supply (1.5V)
65
Figure 16
are:
Functional Description
V1.0, 2008-04
TC1796