MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 213

• Manufacturer Part Number: MCHC908GR8AVFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TOVx — Toggle On Overflow Bit
CHxMAX — Channel x Maximum Duty Cycle Bit
Freescale Semiconductor
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
MSxB
X
X
0
0
0
0
0
0
0
1
1
1
Before enabling a TIM channel register for input capture operation, make
sure that the PTD/TCHx pin is stable for at least two bus clocks.
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
The 100% PWM duty cycle is defined as a continuous high level if the PWM
polarity is 1 and a continuous low level if the PWM polarity is 0. Conversely,
a 0% PWM duty cycle is defined as a continuous low level if the PWM
polarity is 1 and a continuous high level if the PWM polarity is 0.
CHxMAX
MSxA
TCHx
X
X
X
0
1
0
0
0
1
1
1
1
OVERFLOW
ELSxB
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
0
0
0
1
1
0
0
1
1
0
1
1
Table 17-3. Mode, Edge, and Level Selection
Figure 17-12
COMPARE
PERIOD
OUTPUT
ELSxA
Figure 17-12. CHxMAX Latency
OVERFLOW
0
0
1
0
1
0
1
0
1
1
0
1
Output compare
shows, the CHxMAX bit takes effect in the cycle after it is set
Buffered output
buffered PWM
Output preset
Input capture
COMPARE
compare or
OUTPUT
or PWM
Mode
NOTE
NOTE
NOTE
OVERFLOW
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
COMPARE
OUTPUT
OVERFLOW
Configuration
COMPARE
OUTPUT
OVERFLOW
I/O Registers
213