MCHC908GR8AVFAE Freescale Semiconductor, MCHC908GR8AVFAE Datasheet - Page 119

• Manufacturer Part Number: MCHC908GR8AVFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the four port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
PTAPUE3–PTAPUE0 — Port A Input Pullup Enable Bits
Freescale Semiconductor
1. X = Don’t care
2. I/O pin pulled up to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
PTAPUE
These writeable bits are software programmable to enable pullup devices on an input port bit.
Bit
X
1 = Corresponding port A pin configured to have internal pullup
0 = Corresponding port A pin has internal pullup disconnected
1
0
Address:
DDRA
Reset:
Read:
Write:
Bit
0
0
1
Figure 12-5. Port A Input Pullup Enable Register (PTAPUE)
DD
$000D
by internal pullup device
Bit 7
0
0
PTA
X
Bit
X
X
(1)
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
= Unimplemented
6
0
0
Input, Hi-Z
Input, V
Table 12-2. Port A Pin Functions
I/O Pin
Output
Mode
DD
5
0
0
(2)
(4)
Table 12-2
Accesses to DDRA
4
0
0
DDRA3–DDRA0
DDRA3–DDRA0
DDRA3–DDRA0
Read/Write
PTAPUE3
summarizes the operation of the port A pins.
3
0
PTAPUE2
2
0
PTA3–PTA0
Read
PTAPUE1
Pin
Pin
1
0
Accesses to PTA
PTAPUE0
Bit 0
0
PTA3–PTA0
PTA3–PTA0
PTA3–PTA0
Write
Port A
(3)
(3)
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