MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 61

• Manufacturer Part Number: MC68HC908LB8CPE
• Description: IC MCU 8K FLASH 8MHZ 20DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908LB8CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVR, POR, PWM
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

COPRS — COP Rate Select Bit
LVISTOP — LVI Enable in Stop Mode Bit
LVIRSTD — LVI Reset Disable Bit
LVIPWRD — LVI Power Disable Bit
SSREC — Short Stop Recovery Bit
Freescale Semiconductor
COPD selects the COP timeout period. Reset clears COPRS. See
Properly (COP) Module
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
LVIRSTD disables the reset signal from the LVI module. See
LVIPWRD disables the LVI module. See
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a
4096-BUSCLKX4 cycle delay.
If running with external crystal, it is advisable to set the short stop recovery bit to 0. The short stop
recovery does not provide enough time for oscillator stabilization and for this reason the SSREC bit
should not be set.
When using the LVI during normal operation but disabling during stop mode, the LVI will have an
enable time of t
BUSCLKX4 cycles) gives a delay longer than the LVI enable time for these startup scenarios. There
is no period where the MCU is not protected from a low-power condition. However, when using the
short stop recovery configuration option, the 32-BUSCLKX4 delay must be greater than the LVI’s turn
on time to avoid a period in startup where the LVI is not protecting the MCU.
1 = COP timeout period = 2
0 = COP timeout period = 2
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1 = LVI module resets disabled
0 = LVI module resets enabled
1 = LVI module power disabled
0 = LVI module power enabled
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
Address:
Exiting stop mode by an LVI reset will result in the long stop recovery.
Reset:
Read:
Write:
EN
. The system stabilization time for power-on reset and long stop recovery (both 4096
COPRS
$001F
Bit 7
0
Figure 5-2. Configuration Register 1 (CONFIG1)
= Unimplemented
LVISTOP
13
18
6
0
– 2
– 2
MC68HC908LB8 Data Sheet, Rev. 1
4
4
LVIRSTD
BUSCLKX4 cycles
BUSCLKX4 cycles
5
0
Chapter 12 Low-Voltage Inhibit
LVIPWRD
NOTE
4
0
3
0
0
Chapter 12 Low-Voltage Inhibit
SSREC
2
0
Chapter 6 Computer Operating
(LVI).
STOP
1
0
Functional Description
COPD
Bit 0
0
(LVI).
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