MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 175

• Manufacturer Part Number: MC68HC908LB8CPE
• Description: IC MCU 8K FLASH 8MHZ 20DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908LB8CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVR, POR, PWM
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

See
or POR. See
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
17.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 BUSCLKX4 cycles. Thirty-two BUSCLKX4 cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
At power-on, these events occur:
Freescale Semiconductor
•
•
•
•
•
•
Figure
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive BUSCLKX4.
Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow
stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
17-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI,
Figure
BUSCLKX4
For LVI or POR resets, the SIM cycles through 4096 + 32 BUSCLKX4
cycles during which the SIM forces the RST pin low. The internal reset
signal then follows the sequence from the falling edge of RST shown in
Figure
IRST
RST
IAB
17-6.
17-5.
Figure 17-6. Sources of Internal Reset
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
Figure 17-5. Internal Reset Timing
RST PULLED LOW BY MCU
MC68HC908LB8 Data Sheet, Rev. 1
MODRST
32 CYCLES
COPRST
POR
LVI
NOTE
INTERNAL RESET
32 CYCLES
VECTOR HIGH
Reset and System Initialization
175