MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 178
MC68HC908LB8CPE
Manufacturer Part Number
MC68HC908LB8CPE
Description
IC MCU 8K FLASH 8MHZ 20DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908LB8CDWE.pdf
(234 pages)
Specifications of MC68HC908LB8CPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVR, POR, PWM
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908LB8CPE
Manufacturer:
IR
Quantity:
10
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System Integration Module (SIM)
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See
17.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first.
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
178
INTERRUPT
I BIT
INTERRUPT
R/W
I BIT
IDB
R/W
IAB
IDB
IAB
MODULE
MODULE
Figure 17-11
DUMMY
DUMMY
SP – 4
SP
demonstrates what happens when two interrupts are pending. If an interrupt
PC – 1[7:0] PC – 1[15:8]
CCR
Figure 17-9. Interrupt Recovery Timing
Figure 17-8
SP – 3
SP – 1
MC68HC908LB8 Data Sheet, Rev. 1
A
SP – 2
SP – 2
.
Interrupt Entry Timing
X
X
Figure
SP – 1
SP – 3
PC – 1 [7:0] PC – 1 [15:8] OPCODE
17-10.
A
SP – 4
SP
CCR
VECT H
PC
V DATA H
PC + 1
VECT L
OPERAND
V DATA L
START ADDR
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