MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 133

• Manufacturer Part Number: MC68HC908LB8CPE
• Description: IC MCU 8K FLASH 8MHZ 20DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908LB8CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVR, POR, PWM
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Chapter 14
Input/Output (I/O) Ports
14.1 Introduction
Bidirectional input-output (I/O) pins form three parallel ports. All I/O pins are programmable as inputs or
outputs. All individual bits within port A and port C are software configurable with pullup devices if
configured as input port bits. The pullup devices are automatically and dynamically disabled when a port
bit is switched to output mode.
Freescale Semiconductor
Addr.
$0000
$0001
$0002
$0004
$0005
$0006
Data Direction Register C
Data Direction Register A
Data Direction Register B
Register Name
Port C Data Register
Port A Data Register
Port B Data Register
Connect any unused I/O pins to an appropriate logic level, either V
V
termination reduces excess current consumption and the possibility of
electrostatic damage.
SS
See page 134.
See page 136.
See page 138.
See page 135.
See page 137.
See page 139.
. Although the I/O ports do not require termination for proper operation,
(DDRA)
(DDRB)
(DDRC)
(PTA)
(PTB)
(PTC)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Figure 14-1. I/O Port Register Summary
DDRB7
PTB7
Bit 7
0
0
0
0
0
0
0
0
MC68HC908LB8 Data Sheet, Rev. 1
= Unimplemented
DDRA6
DDRB6
PTA6
PTB6
6
0
0
0
0
0
0
NOTE
DDRA5
DDRB5
PTA5
PTB5
5
0
0
0
0
0
0
DDRA4
DDRB4
Unaffected by reset
Unaffected by reset
PTA4
PTB4
4
0
0
0
0
0
0
DDRA3
DDRB3
PTA3
PTB3
3
0
0
0
0
0
0
DDRA2
DDRB2
PTC2
PTA2
PTB2
2
0
0
0
0
0
DD
or
DDRA1
DDRB1
DDRC1
PTC1
PTA1
PTB1
1
0
0
0
0
DDRA0
DDRB0
DDRC0
PTC0
PTA0
PTB0
Bit 0
0
0
0
0
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