MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 164

• Manufacturer Part Number: MC68HC908LB8CPE
• Description: IC MCU 8K FLASH 8MHZ 20DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908LB8CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVR, POR, PWM
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Resets and Interrupts
16.2.3.2 Computer Operating Properly (COP) Reset
A computer operating properly (COP) reset is an internal reset caused by an overflow of the COP counter.
A COP reset sets the COP bit in the SIM reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
16.2.3.3 Low-Voltage Inhibit (LVI) Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the
LVI
An LVI reset:
16.2.3.4 Illegal Opcode Reset
An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal
opcode reset sets the ILOP bit in the SIM reset status register.
If the stop enable bit, STOP, in the CONFIG1 register is a 0, the STOP instruction causes an illegal
opcode reset.
16.2.3.5 Illegal Address Reset
An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal
address reset sets the ILAD bit in the SIM reset status register.
A data fetch from an unmapped address does not generate a reset.
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TRIPF
Releases the RST pin 32 BUSCLKX4 cycles after the oscillator stabilization delay
Sets the POR bit in the SIM reset status register and clears all other bits in the register
Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
BUSCLKX4 cycles after the power supply voltage rises to the LVI
Drives the RST pin low for as long as V
stabilization delay
Sets the LVI bit in the SIM reset status register
voltage.
BUSCLKX4
BUSCLKX2
PORRST
1. PORRST is an internally generated power-on reset pulse.
RST PIN
OSC1
(1)
Figure 16-1. Power-On Reset Recovery
CYCLES
4096
MC68HC908LB8 Data Sheet, Rev. 1
CYCLES
32
DD
is below the LVI
TRIPF
voltage and during the oscillator
TRIPF
voltage
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