HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 259
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 8.4.4, Wait
State Control Register 2 (WCR2)
The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing
shown in figure 8.9.
When software wait insertion is specified by WCR2, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 8.10. A 2-cycle wait is specified as a software
wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the
WAIT signal has no effect if asserted in the T1 cycle or the first Tw cycle.
When the WAITSEL bit in the WCR1 register is set to 1, the WAIT signal is sampled at the
falling edge of the clock. If the setup time and hold times with respect to the falling edge of the
clock are not satisfied, the value sampled at the next falling edge is used.
Read
Write
Figure 8.9 Basic Interface Wait Timing (Software Wait Only)
CKIO
A25 to A0
CSn
RD/WR
RD
D31 to D0
WEn
D31 to D0
BS
T1
Rev. 5.00 May 29, 2006 page 209 of 698
Tw
Section 8 Bus State Controller (BSC)
T2
REJ09B0146-0500
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