HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 218

IC SUPERH MPU ROMLESS 176LQFP

HD6417706F133

Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417706F133

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417706F133
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6417706F133V
Manufacturer:
EDISON
Quantity:
2 000
Part Number:
HD6417706F133V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417706F133V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD6417706F133V
Quantity:
27
Section 8 Bus State Controller (BSC)
Table 8.2
Notes: 1. Memory with interface such as SRAM or ROM.
Rev. 5.00 May 29, 2006 page 168 of 698
REJ09B0146-0500
Area
0
1
2
3
4
5
6
7 *
7
2. Use external pin to specify memory bus width.
3. Use register to specify memory bus width.
4. With synchronous DRAM interfaces, bus width must be 16 or 32 bits.
5. With synchronous DRAM interfaces, bus width must be 16 or 32 bits.
6. With PCMCIA interface, bus width must be 8 or 16 bits.
7. Do not access the reserved area. If the reserved area is accessed, the correct
8. When the control register in area 1 is not used for address translation by the MMU, set
Connectable Memory Physical Address
Ordinary memory *
burst ROM
Internal I/O registers *
Ordinary memory *
synchronous DRAM
Ordinary memory *
synchronous DRAM
Ordinary memory *
Ordinary memory *
PCMCIA, burst ROM
Ordinary memory *
PCMCIA, burst ROM
Reserved area
operation cannot be guaranteed.
the top three bits of the logical address to 101 to allocate in the P2 space.
Physical Address Space Map
1
1
1
1
1
1
,
,
,
,
,
8
H'00000000 to H'03FFFFFF
H'00000000 + H'20000000
H'03FFFFFF + H'20000000
H'04000000 to H'07FFFFFF
H'04000000 + H'20000000
H'07FFFFFF + H'20000000
H'08000000 to H'0BFFFFFF
H'08000000 + H'20000000
H'0BFFFFFF + H'20000000
H'0C000000 to H'0FFFFFFF
H'0C000000 + H'20000000
H'0FFFFFFF + H'20000000
H'10000000 to H'13FFFFFF
H'10000000 + H'20000000
H'13FFFFFF + H'20000000
H'14000000 to H'15FFFFFF
H'16000000 to H'17FFFFFF
H'14000000 + H'20000000
H'17FFFFFF + H'20000000
H'18000000 to H'19FFFFFF
H'1A000000 to H'1BFFFFFF
H'18000000 + H'20000000
H'1BFFFFFF + H'20000000
H'1C000000 + H'20000000
to H'1FFFFFFF + H'20000000
n to
n to
n to
n to
n to
n to
n to
n
n
n
n
n
n
n
n
n
Capacity
64 Mbytes
Shadow
64 Mbytes
Shadow
64 Mbytes
Shadow
64 Mbytes
Shadow
64 Mbytes
Shadow
32 Mbytes
32 Mbytes
Shadow
32 Mbytes
Shadow
Access Size
8, 16, 32 *
n: 1 to 6
8, 16, 32 *
n: 1 to 6
8, 16, 32 *
n: 1 to 6
8, 16, 32 *
n: 1 to 6
8, 16, 32 *
n: 1 to 6
8, 16, 32 *
n: 1 to 6
8, 16, 32 *
n: 1 to 6
n: 0 to 7
2
3
3
3
3
3
3
*
*
*
*
4
5
6
6

Related parts for HD6417706F133