HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 139

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.2.4
The TRAPA exception register (TRA) contains 8-bit immediate data (imm) for the TRAPA
instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA
can also be modified by software.
4.3
4.3.1
The reset sequence is used to power up or restart the SH7706 from the initialization state. The
RESETP signal and RESETM signal are sampled every clock cycle, and in the case of a power-on
reset, all processing being executed (excluding the RTC) is suspended, all unfinished events are
canceled, and reset processing is executed immediately. In the case of a manual reset, however,
reset processing is executed after memory access in progress is completed. The reset sequence
consists of the following operations:
1. The MD bit in SR is set to 1 to place the SH7706 in privileged mode.
2. The BL bit in SR is set to 1, masking any subsequent exceptions.
3. The RB bit in SR is set to 1.
4. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11
5. Instruction execution jumps to the user-written exception handler at address H'A0000000.
Bit
31 to 10
9 to 2
1, 0
to 0 of the EXPEVT register to identify the exception event.
TRAPA Exception Register (TRA)
Operation
Reset
Bit Name
imm
Initial Value R/W
All 0
All 0
R/W
R
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
8-bit immediate data
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 5.00 May 29, 2006 page 89 of 698
Section 4 Exception Processing
REJ09B0146-0500