HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 174

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 6 Interrupt Controller (INTC)
6.4.1
The interrupt priority level setting registers A to E (IPRA to IPRE) are 16-bit read/write registers
that set priority levels from 0 to 15 for on-chip peripheral module interrupts. These registers are
initialized to H'0000 at power-on reset, manual reset, or in hardware standby mode, but is not
initialized in standby mode.
Table 6.6 lists the relationship between the interrupt sources and the IPRA to IPRE bits.
Table 6.6
Note:
As shown in table 6.6, four sets of on-chip peripheral module, IRQ interrupts are assigned to each
register. 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values
from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F is
priority level 15 (the highest level). A reset initializes IPRA to IPRE to H'0000.
H'0 should be set into bits corresponding to an unused interrupt.
Rev. 5.00 May 29, 2006 page 124 of 698
REJ09B0146-0500
Register
IPRA
IPRB
IPRC
IPRD
IPRE
* These bits are always read as 0. The write value should be 0.
Interrupt Priority Registers A to E (IPRA to IPRE)
Interrupt Request Sources and IPRA to IPRE
Bits 15 to 12
TMU0
WDT
IRQ3
Reserved *
DMAC
TMU1
Reserved *
Bits 11 to 8
REF
IRQ2
Reserved *
Bits 7 to 4
TMU2
SCI0
IRQ1
IRQ5
SCIF
Bits 3 to 0
RTC
Reserved *
IRQ0
IRQ4
ADC