HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 131

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.1
Exception processing is separate from normal program processing, and is performed by a routine
separate from the normal program. In response to an exception processing request due to abnormal
termination of the executing instruction, control is passed to a user-written exception handler.
However, in response to an interrupt request, normal program execution continues until the end of
the executing instruction. Here, all exceptions other than resets and interrupts will be called
general exceptions. There are thus three types of exceptions: resets, general exceptions, and
interrupts.
4.1.1
In exception processing, the contents of the program counter (PC) and status register (SR) are
saved in the saved program counter (SPC) and saved status register (SSR), respectively, and
execution of the exception handler is invoked from a vector address. The return from exception
handler (RTE) instruction is issued by the exception handler routine at the completion of the
routine, restoring the contents of the PC and SR to return to the processor state at the point of
interruption and the address where the exception occurred.
A basic exception processing sequence consists of the following operations:
1. The contents of the PC and SR are saved in the SPC and SSR, respectively.
2. The block (BL) bit in SR is set to 1, masking any subsequent exceptions.
3. The mode (MD) bit in SR is set to 1 to place the SH7706 in the privileged mode.
4. The register bank (RB) bit in SR is set to 1.
5. An exception code identifying the exception event is written to bits 11 to 0 of the exception
6. Instruction execution jumps to the designated exception processing vector address to invoke
event (EXPEVT) or interrupt event (INTEVT and INTEVT2) register.
the handler routine.
Exception Processing Flow
Exception Processing Function
Section 4 Exception Processing
Rev. 5.00 May 29, 2006 page 81 of 698
Section 4 Exception Processing
REJ09B0146-0500