HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 109

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
31 to 9
8
7, 6
5, 4
3
2
1
0
Bit Name
SV
RC
TF
IX
AT
Initial
Value
All 0
All 0
All 0
0
0
0
0
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Single virtual memory mode
0: multiple virtual memory mode
1: single virtual memory mode
Reserved
These bits are always read as 0. The write value should
always be 0.
Random counter
A 2-bit random counter, automatically updated by
hardware according to the following rules in the event of
an MMU exception. When a TLB miss exception occurs,
all TLB entry ways corresponding to the virtual address at
which the exception occurred are checked, and if all ways
are valid, 1 is added to RO; if there is one or more invalid
ways, they are set by priority from way 0, in the order:
way 0, way 1, way 2, way 3. In the event of an MMU
exception other than a TLB miss exception, the way
which caused the exception is set in RC.
Reserved
This bit is always read as 0. The write value should
always be 0.
TLB flush
When 1 is set, all valid bits of TLB are cleared to 0 (flush).
This bit is always reads as 0.
Index mode
When 0, VPN bits 16 to 12 are used as the TLB index
number. When 1, the value obtained by EX-ORing ASID
bits 4 to 0 in PTEH and VPN bits 16 to 12 are used as the
TLB index number.
Address translation
Enables (valid) or disables (invalid) the MMU.
0: MMU disabled
1: MMU enabled
Section 3 Memory Management Unit (MMU)
Rev. 5.00 May 29, 2006 page 59 of 698
REJ09B0146-0500