ATTINY167-15MZ Atmel, ATTINY167-15MZ Datasheet - Page 89
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ATTINY167-15MZ
Manufacturer Part Number
ATTINY167-15MZ
Description
MCU AVR 16K FLASH 15MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY167-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY167-15MZ
Manufacturer:
ATMEL
Quantity:
670
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10.2.1
10.3
10.4
7728G–AVR–06/10
Timer/Counter Clock Sources
Counter Unit
Definitions
The following definitions are used extensively throughout the section:
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source is selected by the clock select logic which is controlled by the
clock select (CS02:0) bits located in the Timer/Counter control register (TCCR0).The clock
source clk
ter is written to logic one, the clock source is taken from the Timer/Counter Oscillator
connected to XTAL1 and XTAL2 or directly from XTAL1. For details on asynchronous opera-
tion, see
and prescaler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
ure 10-2
Figure 10-2. Counter Unit Block Diagram
Signal description (internal signals):
BOTTOM
MAX
TOP
count
direction
clear
clk
top
bottom
shows a block diagram of the counter and its surrounding environment.
T
“Asynchronous Status Register – ASSR” on page
T
0
DATA BUS
0 is by default equal to the MCU clock, clk
TCNTn
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in
the count sequence. The TOP value can be assigned to be the fixed value
0xFF (MAX) or the value stored in the OCR0A Register. The assignment is
dependent on the mode of operation.
“Timer/Counter0 Prescaler” on page
direction
Increment or decrement TCNT0 by 1.
Selects between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter0 clock.
Signalizes that TCNT0 has reached maximum value.
Signalizes that TCNT0 has reached minimum value (zero).
count
clear
bottom
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
Prescaler
I/O
. When the AS0 bit in the ASSR Regis-
100.
ATtiny87/ATtiny167
clk
103. For details on clock sources
TnS
Oscillator
clk
I/O
XTAL2
XTAL1
Fig-
89
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