ATTINY167-15MZ Atmel, ATTINY167-15MZ Datasheet - Page 239
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ATTINY167-15MZ
Manufacturer Part Number
ATTINY167-15MZ
Description
MCU AVR 16K FLASH 15MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY167-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY167-15MZ
Manufacturer:
ATMEL
Quantity:
670
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21.8.1
7728G–AVR–06/10
Serial Programming Algorithm
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATtiny87/167, data is clocked on the rising edge of SCK.
When reading data from the ATtiny87/167, data is clocked on the falling edge of SCK. See
Figure 21-7
To program and verify the ATtiny87/167 in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte
5. A: The EEPROM array is programmed one byte at a time by supplying the address
6. Any memory location can be verified by using the Read instruction which returns the
Apply power between Vcc and GND while RESET and SCK are set to “0”. In some
systems, the programmer can not guarantee that SCK is held low during power-up. In
this case, RESET must be given a positive pulse of at least two CPU clock cycles
duration after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not,
all four bytes of the instruction must be transmitted. If the 0x53 did not echo back,
give RESET a positive pulse and issue a new Programming Enable command.
at a time by supplying the 5 LSB of the address and data together with the Load Pro-
gram memory Page instruction. To ensure correct loading of the page, the data low
byte must be loaded before data high byte is applied for a given address. The Pro-
gram memory Page is stored by loading the Write Program memory Page instruction
with the 6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at
least t
programming interface before the Flash write operation completes can result in incor-
rect programming.
and data together with the appropriate Write instruction. An EEPROM memory loca-
tion is first automatically erased before new data is written. If polling (RDY/BSY) is not
used, the user must wait at least t
21-14) In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is
loaded one byte at a time by supplying the 2 LSB of the address and data together
with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is
stored by loading the Write EEPROM Memory Page Instruction with the 6 MSB of the
address. When using EEPROM page access only byte locations loaded with the
Load EEPROM Memory Page instruction is altered. The remaining locations remain
unchanged. If polling (RDY/BSY) is not used, the used must wait at least t
before issuing the next page (See
the data file(s) need to be programmed.
content at the selected address at serial output MISO.
and
WD_FLASH
Figure 21-8
before issuing the next page. (See
for timing details.
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
WD_EEPROM
Table
21-8). In a chip erased device, no 0xFF in
before issuing the next byte. (See
ATtiny87/ATtiny167
Table
21-14) Accessing the serial
Table 21-15 on page
ck
ck
>= 12 MHz
>= 12 MHz
WD_EEPROM
Table
240):
239
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