ATTINY167-15MZ Atmel, ATTINY167-15MZ Datasheet - Page 39
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ATTINY167-15MZ
Manufacturer Part Number
ATTINY167-15MZ
Description
MCU AVR 16K FLASH 15MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY167-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY167-15MZ
Manufacturer:
ATMEL
Quantity:
670
- Current page: 39 of 283
- Download datasheet (5Mb)
4.5.3
7728G–AVR–06/10
CLKCSR – Clock Control & Status Register
Table 4-10.
• Bit 7 – CLKCCE: Clock Control Change Enable
The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The
CLKCCE bit is only updated when the other bits in CLKCSR are simultaneously written to
zero. CLKCCE is cleared by hardware four cycles after it is written or when the CLKCSR bits
are written. Rewriting the CLKCCE bit within this time-out period does neither extend the
time-out period, nor clear the CLKCCE bit.
• Bits 6:5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny87/167 and will always read as zero.
• Bits 4 – CLKRDY: Clock Ready Flag
This flag is the output of the ‘Clock Availability ’ logic.
This flag is cleared by the ‘Request for Clock Availability’ command or ‘Enable Clock Source’
command being entered.
It is set when ‘Clock Availability’ logic confirms that the (selected) clock is running and is sta-
ble. The delay from the request and the flag setting is not fixed, it depends on the clock
Bit
Read/Write
Initial Value
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLKCCE
Clock Prescaler Select
R/W
7
0
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
6
–
R
0
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R
5
–
0
CLKRDY
R
4
0
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKC3
R/W
3
0
ATtiny87/ATtiny167
CLKC2
R/W
2
0
Clock Division Factor
CLKC1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
128
256
16
32
64
1
2
4
8
CLKC0
R/W
0
0
CLKCSR
39
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