ATTINY167-15MZ Atmel, ATTINY167-15MZ Datasheet - Page 75

• Manufacturer Part Number: ATTINY167-15MZ
• Description: MCU AVR 16K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.1
9.3.2
7728G–AVR–06/10
MCU Control Register – MCUCR
Port Control Register – PORTCR
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0, 1). See
figuring the Pin” on page 68
• Bits 5, 4 – BBMx: Break-Before-Make Mode Enable
When these bits are written to one, the port-wise Break-Before-Make mode is activated. The
intermediate tri-state cycle is then inserted when writing DDRxn to make an output. For further
information, see
• Bits 1, 0 – PUDx: Port-Wise Pull-up Disable
When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled
even if the DDxn and PORTxn Registers are configured to enable the pull-ups
({DDxn, PORTxn} = 0, 1). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up
Disable bit (PUD) from the MCUCR register. See
details about this feature.
Initial Value
Initial Value
Read/Write
Read/Write
Bit
Bit
R/W
7
–
R
0
7
0
-
“Break-Before-Make Switching” on page
BODS
R/W
R/W
6
0
6
0
-
for more details about this feature.
BODSE
BBMB
R/W
R/W
5
0
5
0
BBMA
PUD
R/W
R/W
4
0
4
0
“Configuring the Pin” on page 68
R/W
R
3
–
0
3
0
-
ATtiny87/ATtiny167
69.
R/W
R
2
–
0
2
0
-
PUDB
R/W
R
1
–
0
1
0
PUDA
R/W
R
0
–
0
0
0
for more
PORTCR
MCUCR
“Con-
75