ATTINY167-15MZ Atmel, ATTINY167-15MZ Datasheet - Page 138
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ATTINY167-15MZ
Manufacturer Part Number
ATTINY167-15MZ
Description
MCU AVR 16K FLASH 15MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY167-15MZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY167-15MZ
Manufacturer:
ATMEL
Quantity:
670
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12.11.8
12.11.9
138
ATtiny87/ATtiny167
Input Capture Register – ICR1H and ICR1L
Timer/Counter1 Interrupt Mask Register – TIMSK1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on
the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input
Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are
read simultaneously when the CPU accesses these registers, the access is performed using
an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other
16-bit registers.
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICIE1: Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
located in TIFR1, is set.
• Bit 4..3 – Reserved Bits
These bits are reserved for future use.
• Bit 2 – OCIE1B: Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The correspond-
ing Interrupt Vector
the OCF1B flag, located in TIFR1, is set.
• Bit 1 – OCIE1A: Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The correspond-
ing Interrupt Vector
the OCF1A flag, located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vec-
tor
located in TIFR1, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See ”Interrupt Vectors in ATtiny87/167” on page
(See ”Interrupt Vectors in ATtiny87/167” on page
R/W
See “Accessing 16-bit Registers” on page 112.
R
7
0
7
–
0
(See ”Interrupt Vectors in ATtiny87/167” on page
(See ”Interrupt Vectors in ATtiny87/167” on page
R/W
R
6
0
6
–
0
ICIE1
R/W
R/W
5
0
5
0
R/W
R
4
–
0
4
0
ICR1[15:8]
ICR1[7:0]
R/W
R
3
–
0
3
0
59.) is executed when the TOV1 flag,
59.) is executed when the ICF1 flag,
OCIE1B
R/W
R/W
2
0
2
0
OCIE1A
R/W
R/W
1
0
1
0
59.) is executed when
59.) is executed when
TOIE1
R/W
R/W
0
0
0
0
7728G–AVR–06/10
TIMSK1
ICR1H
ICR1L
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