ATTINY167-15MZ Atmel, ATTINY167-15MZ Datasheet - Page 119

• Manufacturer Part Number: ATTINY167-15MZ
• Description: MCU AVR 16K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.7
7728G–AVR–06/10
Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1A/B). If TCNT equals OCR1A/B the comparator signals a match. A match will set the
Output Compare Flag (OCF1A/B) at the next timer clock cycle. If enabled (OCIE1A/B = 1), the
Output Compare Flag generates an Output Compare interrupt. The OCF1A/B flag is automati-
cally cleared when the interrupt is executed. Alternatively the OCF1A/B flag can be cleared by
software by writing a logical one to its I/O bit locations. The Waveform Generator uses the
match signal to generate an output according to operating mode set by the Waveform Gener-
ation mode (WGM13:0) bits and Compare Output mode (COM1A/B1:0) bits. The TOP and
BOTTOM signals are used by the Waveform Generator for handling the special cases of the
extreme values in some modes of operation
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value
(i.e., counter resolution). In addition to the counter resolution, the TOP value defines the
period time for waveforms generated by the Waveform Generator.
Figure 12-4
gram that are not directly a part of the Output Compare unit are gray shaded.
Figure 12-4. Output Compare Unit, Block Diagram
The OCR1A/B Register is double buffered when using any of the twelve Pulse Width Modula-
tion (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR1A/B Compare Register to either TOP or BOTTOM of the counting sequence. The syn-
chronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
shows a block diagram of the Output Compare unit. The elements of the block dia-
OCRnxH Buf.(8-bit)
OCRnxH (8-bit)
BOTTOM
OCRnx Buffer (16-bit Register)
TEMP (8-bit)
TOP
OCRnx (16-bit Register)
OCRnxL Buf.(8-bit)
OCRnxL (8-bit)
DATA BUS
(See “Modes of Operation” on page
Waveform Generator
WGMn3:0
=
(16-bit Comparator )
(8-bit)
COMnx1:0
ATtiny87/ATtiny167
TCNTnH (8-bit)
OCFnx
TCNTn (16-bit Counter)
(Int.Req.)
TCNTnL (8-bit)
122.)
OCnxW
OCnxX
OCnxU
OCnxV
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