ATTINY167-15MZ Atmel, ATTINY167-15MZ Datasheet - Page 107

• Manufacturer Part Number: ATTINY167-15MZ
• Description: MCU AVR 16K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11. Timer/Counter1 Prescaler
11.1
11.1.1
11.1.2
11.1.3
7728G–AVR–06/10
Overview
Internal Clock Source
Prescaler Reset
External Clock Source
Most bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
used as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the
state of the prescaler will have implications for situations where a prescaled clock is used. One
example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler
(6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the
first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler
divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it
is connected to.
An external clock source applied to the T1 pin can be used as Timer/Counter clock (clk
The T1 pin is sampled once every system clock cycle by the pin synchronization logic. The
synchronized (sampled) signal is then passed through the edge detector.
functional equivalent block diagram of the T1 synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (
transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 11-1. T1 Pin Sampling
CLK_I/O
/256, or f
Tn
clk
I/O
CLK_I/O
D
LE
Q
/1024.
Synchronization
CLK_I/O
D
Q
). Alternatively, one of four taps from the prescaler can be
T1
pulse for each positive (CSn2:0 = 7) or negative
D
ATtiny87/ATtiny167
Q
Edge Detector
CLK_I/O
Figure 11-1
clk
Select Logic)
(To Clock
I/O
Tn_sync
/8, f
). The latch is
CLK_I/O
shows a
T
/64,
107
1).