ATMEGA165-16AI Atmel, ATMEGA165-16AI Datasheet - Page 79

• Manufacturer Part Number: ATMEGA165-16AI
• Description: IC AVR MCU 16K 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Compare Match Output
Unit
Compare Output Mode and
Waveform Generation
2573G–AVR–07/09
The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Gener-
ator uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next
compare match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 30
shows a simplified schematic of the logic affected by the COM0A1:0 bit setting. The I/O
Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the
general I/O port control registers (DDR and PORT) that are affected by the COM0A1:0
bits are shown. When referring to the OC0A state, the reference is for the internal OC0A
Register, not the OC0A pin. If a System Reset occur, the OC0A Register is reset to “0”.
Figure 30. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0A) from the
Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin
direction (input or output) is still controlled by the Data Direction Register (DDR) for the
port pin. The Data Direction Register bit for the OC0A pin (DDR_OC0A) must be set as
output before the OC0A value is visible on the pin. The port override function is indepen-
dent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0A state
before the output is enabled. Note that some COM0A1:0 bit settings are reserved for
certain modes of operation. See “8-bit Timer/Counter Register Description” on page 85.
The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and
PWM modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator
that no action on the OC0A Register is to be performed on the next compare match. For
compare output actions in the non-PWM modes refer to Table 43 on page 86. For fast
PWM mode, refer to Table 44 on page 86, and for phase correct PWM refer to Table 45
on page 87.
A change of the COM0A1:0 bits state will have effect at the first compare match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect
by using the FOC0A strobe bits.
COMnx1
COMnx0
FOCn
clk
I/O
Waveform
Generator
D
D
PORT
D
DDR
OCnx
Q
Q
Q
1
0
ATmega165/V
OCn
Pin
79