ATMEGA165-16AI Atmel, ATMEGA165-16AI Datasheet - Page 166

• Manufacturer Part Number: ATMEGA165-16AI
• Description: IC AVR MCU 16K 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

USART Register
Description
USART I/O Data Register –
UDR
USART Control and Status
Register A – UCSRA
2573G–AVR–07/09
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers
share the same I/O address referred to as USART Data Register or UDR. The Transmit
Data Buffer Register (TXB) will be the destination for data written to the UDR Register
location. Reading the UDR Register location will return the contents of the Receive Data
Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter
and set to zero by the Receiver.
The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is
set. Data written to UDR when the UDRE Flag is not set, will be ignored by the USART
Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled,
the Transmitter will load the data into the Transmit Shift Register when the Shift Register
is empty. Then the data will be serially transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever
the receive buffer is accessed. Due to this behavior of the receive buffer, do not use
Read-Modify-Write instructions (SBI and CBI) on this location. Be careful when using bit
test instructions (SBIC and SBIS), since these also will change the state of the FIFO.
• Bit 7 – RXC: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty (i.e., does not contain any unread data). If the Receiver is dis-
abled, the receive buffer will be flushed and consequently the RXC bit will become zero.
The RXC Flag can be used to generate a Receive Complete interrupt (see description of
the RXCIE bit).
• Bit 6 – TXC: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted
out and there are no new data currently present in the transmit buffer (UDR). The TXC
Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can
be cleared by writing a one to its bit location. The TXC Flag can generate a Transmit
Complete interrupt (see description of the TXCIE bit).
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
RXC
R/W
7
0
R
7
0
R/W
TXC
R/W
6
0
6
0
UDRE
R/W
5
0
R
5
1
R/W
4
0
FE
R
4
0
RXB[7:0]
TXB[7:0]
R/W
DOR
3
0
3
R
0
R/W
UPE
2
0
R
2
0
ATmega165/V
R/W
1
0
U2X
R/W
1
0
R/W
MPCM
0
0
R/W
0
0
UDR (Write)
UDR (Read)
UCSRA
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