ATMEGA165-16MI Atmel, ATMEGA165-16MI Datasheet
ATMEGA165-16MI
Specifications of ATMEGA165-16MI
Related parts for ATMEGA165-16MI
ATMEGA165-16MI Summary of contents
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... I/O and Packages – 53 Programmable I/O Lines2573GS – 64-lead TQFP and 64-pad QFN/MLF • Speed Grade: – ATmega165V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega165 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...
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... Pin Configurations Disclaimer 2573GS–AVR–07/09 Figure 1. Pinout ATmega165 DNC 1 (RXD/PCINT0) PE0 2 INDEX CORNER (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 13 (OC0A/PCINT12) PB4 14 (OC1A/PCINT13) PB5 15 (OC1B/PCINT14) PB6 ...
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... Overview The ATmega165 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega165 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2 ...
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... In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega165 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega165 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir- cuit Emulators, and Evaluation kits. ...
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... The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega165 as listed on page 66. Port F serves as the analog inputs to the A/D Converter. ...
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... The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega165 as listed on page 66. Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running ...
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... USART I/O Data Register USART Baud Rate Register Low – – – – UMSEL UPM1 UPM0 USBS TXCIE UDRIE RXEN TXEN TXC UDRE FE DOR ATmega165/V Bit 2 Bit 1 Bit 0 – – – – – – – – – – – – – – ...
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... FOC1B – – ICES1 – WGM13 WGM12 COM1A0 COM1B1 COM1B0 – – – ADC6D ADC5D ADC4D ADC3D ATmega165/V Bit 2 Bit 1 Bit 0 – – – – – – – – – – – – – – – – – ...
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... EEPROM Address Register Low Byte EEPROM Data Register – – – EERIE General Purpose I/O Register 0 PCIE0 – – PCIF0 – – ATmega165/V Bit 2 Bit 1 Bit 0 – – – – MUX2 MUX1 MUX0 – ADTS2 ADTS1 ADTS0 ADPS2 ...
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... When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega165 is a com- plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...
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... PC ← then PC ← then PC ← then PC ← then PC ← ⊕ then PC ← ⊕ then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ATmega165/V Operation Flags #Clocks Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V ...
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... Y ← (Y) ← ← Rr (Z) ← Rr (Z) ← Rr, Z ← ← (Z) ← ← Rr (k) ← ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 (Z) ← R1:R0 Rd ← ← Rr STACK ← Rr ATmega165/V Operation Flags #Clocks None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None ...
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... MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 2573GS–AVR–07/09 Description Rd ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only ATmega165/V Operation Flags #Clocks None None None None None N/A 13 ...
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... Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 64M1 2573GS–AVR–07/09 Ordering Code Package ATmega165V-8AI 64A (2) ATmega165V-8AU 64A ATmega165V-8MI 64M1 (2) ATmega165V-8MU 64M1 ATmega165-16AI 64A (2) ATmega165-16AU 64A ATmega165-16MI 64M1 (2) ATmega165-16MU 64M1 Package Type ATmega165/V (1) Operation Range Industrial 0°C to 85°C) (-4 Industrial 0°C to 85°C) (-4 14 ...
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... Orchard Parkway San Jose, CA 95131 R 2573GS–AVR–07/09 B PIN 1 IDENTIFIER TITLE 64A, 64-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega165/V A COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM NOTE A – – 1.20 A1 0.05 – ...
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... Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 64M1, 64-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) ATmega165/V C SEATING PLANE A1 A 0.08 C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE SYMBOL A 0 ...
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... Errata ATmega165 Rev A 2573GS–AVR–07/09 • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00 ...
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... Updated C Code Example in “USART Initialization” on page 152 5. Moved “Table 106 on page 248” and “Table 107 on page 248” to “Page Size” on page 248. 6. Updated “Register Summary” on page 7 7. Updated Figure 115 on page 255. 8. Updated “Ordering Information” on page 14 ATmega165/V 18 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...