ATMEGA165-16AI Atmel, ATMEGA165-16AI Datasheet
ATMEGA165-16AI
Specifications of ATMEGA165-16AI
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ATMEGA165-16AI Summary of contents
Page 1
... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Speed Grade: – ATmega165V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega165 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...
Page 2
... Pin Configurations Disclaimer 2573G–AVR–07/09 Figure 1. Pinout ATmega165 DNC 1 (RXD/PCINT0) PE0 2 INDEX CORNER (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 13 (OC0A/PCINT12) PB4 14 (OC1A/PCINT13) PB5 15 (OC1B/PCINT14) PB6 ...
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... Overview The ATmega165 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega165 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2 ...
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... In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega165 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega165 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir- cuit Emulators, and Evaluation kits. ...
Page 5
... The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega165 as listed on page 66. Port F serves as the analog inputs to the A/D Converter. ...
Page 6
... The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega165 as listed on page 66. Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running ...
Page 7
... The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typical ALU operation, two operands are output from the Register File, ATmega165/V Data Bus 8-bit Status ...
Page 8
... Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega165 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
Page 9
... The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATmega165 ...
Page 10
... Data Space. Although not being phys- ically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. ATmega165/V 0 Addr. R0 ...
Page 11
... AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit – – – SP7 SP6 SP5 Read/Write R/W R/W R/W R/W R/W R/W Initial Value ATmega165 R26 (0x1A R28 (0x1C R30 (0x1E – – SP10 SP9 SP4 SP3 SP2 SP1 4 ...
Page 12
... External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 46 for more information. The Reset Vector can also be ATmega165/V , directly generated from the selected clock CPU ...
Page 13
... EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ ATmega165/V 13 ...
Page 14
... This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega165/V 14 ...
Page 15
... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega165 Program Counter (PC bits wide, thus addressing the 8K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...
Page 16
... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Regis- ters, and the 1,024 bytes of internal data SRAM in the ATmega165 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” ...
Page 17
... Data RD Memory Access Instruction The ATmega165 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
Page 18
... X X • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega165 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...
Page 19
... EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU. Table 1. EEPROM Programming Time Symbol Number of Calibrated RC Oscillator Cycles EEPROM write (from CPU) ATmega165/V Typ Programming Time 67 584 8 ...
Page 20
... EEPROM_write(unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } ATmega165/V 20 ...
Page 21
... EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low recommendation: ATmega165/V 21 ...
Page 22
... I/O Memory General Purpose I/O Registers The ATmega165 contains three General Purpose I/O Registers. These registers can be General Purpose I/O Register 2 – GPIOR2 General Purpose I/O Register 1 – GPIOR1 General Purpose I/O Register 0 – GPIOR0 2573G–AVR–07/09 Keep the AVR RESET active (low) during periods of insufficient power supply voltage. ...
Page 23
... The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. ATmega165/V CPU Core RAM clk ...
Page 24
... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 3. The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega165 Typical Characteristics” on page 285. Table 3. Number of Watchdog Oscillator Cycles Typ Time-out ( ...
Page 25
... Notes: 1. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5. ATmega165/V XTAL2 XTAL1 GND Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
Page 26
... SUT Fuses as shown in Table 6 and CKSEL1..0 as shown in Table 7. Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection SUT1..0 Additional Delay from Reset (V 00 14CK 01 14CK + 4 14CK + ATmega165/V Additional Delay from Reset (V = 5.0V) Recommended Usage CC (1) 14CK + 4.1 ms Ceramic resonator, fast rising power (1) ...
Page 27
... Table 9. Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- SUT1..0 down and Power-save ( Note: 1. The device is shipped with this option selected. ATmega165/V Recommended Usage 1K CK Stable frequency at start-up (1) Nominal Frequency 8.0 MHz Additional Delay from Reset (V = 5.0V) Recommended Usage CC 14CK BOD enabled 14CK + 4 ...
Page 28
... Figure 13. To run the device on an external clock, the CKSEL Fuses must be pro- grammed to “0000”. Figure 13. External Clock Drive Configuration NC EXTERNAL CLOCK SIGNAL When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 12. Table 11. Crystal Oscillator Clock Frequency CKSEL3..0 0000 ATmega165 CAL4 CAL3 CAL2 CAL1 R/W R/W R/W ...
Page 29
... The ATmega165 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the require- ment for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
Page 30
... The device is shipped with the CKDIV8 Fuse programmed. Table 13. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 ATmega165/V CLKPS0 Clock Division Factor Reserved 1 0 Reserved 1 1 Reserved 0 0 Reserved ...
Page 31
... From the time the CLKPS values are written, it takes between and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are pro- duced. Here the previous clock period, and T2 is the period corresponding to the new prescaler setting. ATmega165/V CLKPS0 Clock Division Factor 0 ...
Page 32
... If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 11 on page 23 presents the different clock systems in the ATmega165, and their distribution. The figure is helpful in selecting an appropriate sleep mode. The Sleep Mode Control Register contains control bits for power management. ...
Page 33
... Interrupt Enable bit in SREG is set. If Timer/Counter2 is not running, Power-down mode is recommended instead of Power- save mode. The Timer/Counter2 can be clocked both synchronously and asynchronously in Power- save mode. If the Timer/Counter2 is using the asynchronous clock, the Timer/Counter ATmega165/V and clk , while allowing the other clocks to run. FLASH , clk ...
Page 34
... Bit 7..4 - Res: Reserved bits These bits are reserved in ATmega165 and will always read as zero. • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. ...
Page 35
... Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref- erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 186 for details on how to configure the Analog Comparator. ATmega165/V 35 ...
Page 36
... Note that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. ATmega165/V ) are stopped, the input buf- ADC /2, ...
Page 37
... The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 24. The ATmega165 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ) ...
Page 38
... V RESET Pin Threshold Voltage RST Minimum pulse width on t RST RESET Pin Notes: 1. The Power-on Reset will not work unless the supply voltage has been below V (falling) ATmega165/V DATA BUS MCU Status Register (MCUSR) Circuit Delay Counters Clock CK Condition Min Typ T = -40° ...
Page 39
... V CC Figure 15. MCU Start-up, RESET Tied POT RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 16. MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL RESET ATmega165/V rise. The RESET signal is activated CC decreases below the detection level RST t TOUT is below the CC 39 ...
Page 40
... MCU after the Time-out period – t Figure 17. External Reset During Operation CC ATmega165 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection ...
Page 41
... This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset writing a logic zero to the flag. ATmega165/V decreases to a value below the trigger level ( the voltage stays below the trigger level ...
Page 42
... Reset Flags. ATmega165 features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator or the ADC. The voltage reference has a start-up time that may influence the way it should be used. ...
Page 43
... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega165 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
Page 44
... Note:Also see Figure 183 on page 312. ATmega165/V Typical Time-out Typical Time-out 3. 5. 15.4 ms 14.7 ms 30.8 ms 29.3 ms 61.6 ms 58.7 ms 0.12 s 0.12 s 0.25 s 0.23 s 0.49 s 0.47 s 1.0 s 0.9 s 2.0 s 1.9 s ...
Page 45
... In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. ATmega165/V 45 ...
Page 46
... Interrupts Interrupt Vectors in ATmega165 2573G–AVR–07/09 This section describes the specifics of the interrupt handling as performed in ATmega165. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 22. Reset and Interrupt Vectors Vector Program (2) No. Address Source ...
Page 47
... The Boot Reset Address is shown in Table 96 on page 244. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega165 is: Address Labels Code 0x0000 ...
Page 48
... SPH,r16 0x1C02 ldi r16,low(RAMEND) 0x1C03 out SPL,r16 0x1C04 sei 0x1C05 <instr> xxx ATmega165/V Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; PCINT0 Handler ; ; Store Program Memory Ready Handler Comments ; IRQ0 Handler ; PCINT0 Handler ; ; Store Program Memory Ready Handler ...
Page 49
... Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 232 for details on Boot Lock bits. • Bit 0 – IVCE: Interrupt Vector Change Enable ATmega165/V Comments ; Reset handler ; IRQ0 Handler ...
Page 50
... Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret C Code Example void Move_interrupts(void Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); } ATmega165/V 50 ...
Page 51
... SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 23. An example of timing of a pin change interrupt is shown in Figure 21. Figure 21. Pin Change Interrupt pin_lat PCINT( pin_sync LE clk PCINT(0) in PCMSK(x) clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF ATmega165/V pcint_in_(0) 0 pcint_syn pcint_setflag x clk PCIF 51 ...
Page 52
... Table 24. Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request Any logical change on INT0 generates an interrupt request The falling edge of INT0 generates an interrupt request The rising edge of INT0 generates an interrupt request. ATmega165 – – – ISC01 ISC00 R/W R/W ...
Page 53
... If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter- rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. ATmega165 ...
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... Each PCINT7..0 bit selects whether pin change interrupt is enabled on the correspond- ing I/O pin. If PCINT7..0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATmega165 ...
Page 55
... Most port pins are multiplexed with alternate functions for the peripheral fea- tures on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 60. Refer to the individual module sections for a full description of the alternate functions. ATmega165 Logic See Figure " ...
Page 56
... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an out- put pin, the port pin is driven low (zero). ATmega165/V PUD Q D ...
Page 57
... The maximum and minimum propagation delays are denoted t respectively. Figure 24. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 ATmega165/V I/O Pull-up Comment Input No Tri-state (Hi-Z) Pxn will source current if ext. pulled Input Yes low ...
Page 58
... In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 25. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 ATmega165/V 0xFF nop in r17, PINx 0x00 0xFF ...
Page 59
... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. ATmega165/V 59 ...
Page 60
... WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk , SLEEP, and PUD are common to all ports. All other signals are unique for each I/O pin. ATmega165/V or GND is not recommended, since this may CC (1) PUOExn ...
Page 61
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega165/V Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010 ...
Page 62
... Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external inter- rupt source. ATmega165 PUD – ...
Page 63
... When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced input, the pull-up can still be con- trolled by the PORTB0 bit PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source. ATmega165/V 63 ...
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... OUTPUT OUTPUT PTOE – – DIEOE PCINT11 • PCIE1 PCINT10 • PCIE1 DIEOV PCINT11 INPUT PCINT10 INPUT SPI MSTR INPUT SPI SLAVE INPUT AIO – – ATmega165/V PB5/OC1A/ PB4/OC0A/ PCINT13 PCINT12 OC1A ENABLE OC0A ENABLE OC1A OC0A – – PCINT13 • PCIE1 PCINT12 • ...
Page 65
... Table 31. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PD3 PD2 PUOE 0 0 PUOV 0 0 DDOE 0 0 DDOV 0 0 PVOE 0 0 PVOV 0 0 PTOE – – DIEOE 0 0 DIEOV – – AIO – – ATmega165/V PD1/INT0 PD0/ICP1 – – INT0 ENABLE INT0 ENABLE 0 INT0 INPUT ICP1 INPUT 65 ...
Page 66
... PCINT4, Pin Change Interrupt Source 4: The PE4 pin can serve as an external interrupt source. • AIN1/PCINT3 – Port E, Bit 3 AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. PCINT3, Pin Change Interrupt Source 3: The PE3 pin can serve as an external interrupt source. ATmega165/V 66 ...
Page 67
... PCINT6 • PCIE0 PCIE0 DIEOV PCINT7 PCINT6 INPUT INPUT AIO – – Note: 1. CKOUT is one if the CKOUT Fuse is programmed ATmega165/V PE5/DI/SDA/ PE4/USCK/SCL/ PCINT5 PCINT4 USI_TWO-WIRE USI_TWO-WIRE 0 0 USI_TWO-WIRE USI_TWO-WIRE (SDA + PORTE5) • (USI_SCL_HOLD • DDE5 PORTE4) + DDE4 USI_TWO-WIRE • USI_TWO-WIRE • ...
Page 68
... TDI, ADC7 – Port F, Bit 7 ADC7, Analog to Digital Converter, Channel 7 TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. ATmega165/V PE1/TXD/ PCINT1 TXEN 0 ...
Page 69
... JTAGEN JTAGEN DDOV 0 SHIFT_IR + SHIFT_DR PVOE 0 JTAGEN PVOV 0 TDO PTOE – – DIEOE JTAGEN JTAGEN DIEOV – – AIO TDI ADC6 INPUT ADC7 INPUT ATmega165 PF5/ADC5/TMS PF4/ADC4/TCK JTAGEN JTAGEN 1 1 JTAGEN JTAGEN – – JTAGEN JTAGEN 0 0 – – TMS TCK ...
Page 70
... Alternate Function PG4 T0(Timer/Counter0 Clock Input) PG3 T1(Timer/Counter1 Clock Input) PG2 – PG1 – PG0 – The alternate pin configuration is as follows: • T0 – Port G, Bit 4 T0, Timer/Counter0 Counter Source. • T1 – Port G, Bit 3 T1, Timer/Counter1 Counter Source. ATmega165/V PF1/ADC1 PF0/ADC0 – ...
Page 71
... Table 40. Overriding Signals for Alternate Functions in PG3:0 Signal Name PG3/T1 PG2 PUOE 0 0 PUOV 0 0 DDOE 0 0 DDOV 1 1 PVOE 0 0 PVOV 0 0 PTOE – – DIEOE 0 0 DIEOV INPUT – AIO – – ATmega165/V PG4/ – INPUT – PG1 PG0 – – – – – – 71 ...
Page 72
... R/W Initial Value N/A N/A N/A Bit PORTC7 PORTC6 PORTC5 Read/Write R/W R/W R/W Initial Value Bit DDC7 DDC6 DDC5 Read/Write R/W R/W R/W Initial Value ATmega165 PORTA4 PORTA3 PORTA2 PORTA1 R/W R/W R/W R DDA4 DDA3 DDA2 DDA1 R/W R/W R/W R ...
Page 73
... N/A N/A Bit PORTF7 PORTF6 PORTF5 Read/Write R/W R/W R/W Initial Value Bit DDF7 DDF6 DDF5 Read/Write R/W R/W R/W Initial Value ATmega165 PINC4 PINC3 PINC2 PINC1 R/W R/W R/W R/W N/A N/A N/A N PORTD4 PORTD3 PORTD2 PORTD1 R/W R/W R/W R ...
Page 74
... Read/Write Initial Value Bit – – – Read/Write Initial Value Bit – – – Read/Write Initial Value ATmega165 PINF4 PINF3 PINF2 PINF1 R/W R/W R/W R/W N/A N/A N/A N PORTG4 PORTG3 PORTG2 PORTG1 R/W R/W R/W R DDG4 DDG3 DDG2 ...
Page 75
... Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For the actual placement of I/O pins, refer to “Pinout ATmega165” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 76
... Clear TCNT0 (set all bits to zero). clk Timer/Counter clock, referred to as clk Tn top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). ATmega165/V TOVn (Int.Req.) Clock Select Edge Detector clk clear Tn Control Logic ...
Page 77
... Operation” on page 80.). Figure 29 shows a block diagram of the Output Compare unit. Figure 29. Output Compare Unit, Block Diagram OCRnx top bottom Waveform Generator FOCn ATmega165/V ). clk can be generated from an external or internal T0 is present or not. A CPU write overrides (has T0 DATA BUS TCNTn ...
Page 78
... Output Compare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM0A1:0 bits are not double buffered together with the compare value. Changing the COM0A1:0 bits will take effect immediately. ATmega165/V 78 ...
Page 79
... PWM mode, refer to Table 44 on page 86, and for phase correct PWM refer to Table 45 on page 87. A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0A strobe bits. ATmega165 OCnx ...
Page 80
... TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written ATmega165/V OCnx Interrupt Flag Set (COMnx1 ...
Page 81
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. Figure 32. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period ATmega165/V f clk_I/O = ------------------------------------------------- - ⋅ ⋅ OCRnx ...
Page 82
... PWM mode is shown on Figure 33. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes repre- sent compare matches between OCR0A and TCNT0. ATmega165/V f clk_I/O f ...
Page 83
... OCR0A changes its value from MAX, like in Figure 33. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. ATmega165/V OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set ...
Page 84
... TOVn Figure 36 shows the setting of OCF0A in all modes except CTC mode. Figure 36. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx ATmega165/V T0 MAX BOTTOM /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value ) is therefore BOTTOM + 1 BOTTOM + 1 ...
Page 85
... Modes of oper- ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 42 and “Modes of Operation” on page 80. ATmega165/V TOP BOTTOM TOP ...
Page 86
... Set OC0A on compare match, clear OC0A at BOTTOM, (inverting mode) Note special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 81 for more details. ATmega165/V (1) Update of TOV0 Flag TOP OCR0A at ...
Page 87
... The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0A Register. ATmega165/V ( ...
Page 88
... Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. ATmega165 ...
Page 89
... Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f ATmega165/V ). Alternatively, one of four taps from the pres- CLK_I/O /1024. ...
Page 90
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this pres- caler will affect both timers. ATmega165/V /2.5. clk_I/O (1) ...
Page 91
... A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. For the actual placement of I/O pins, refer to “Pinout ATmega165” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” ...
Page 92
... The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See “Output Compare Units” on page 100.. The compare match event will ATmega165/V (1) TOVn (Int.Req.) ...
Page 93
... PWM11 is changed to WGM11. • CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1C. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. ATmega165/V 93 ...
Page 94
... Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary regis- ter, the main code must disable the interrupts during the 16-bit access. ATmega165/V 94 ...
Page 95
... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. See “About Code Examples” on page 6. The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATmega165/V 95 ...
Page 96
... TCNT1. If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATmega165/V 96 ...
Page 97
... The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and ATmega165/V TOVn (Int.Req.) Clock Select ...
Page 98
... When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. ATmega165/V DATA BUS (8-bit) ...
Page 99
... ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). ATmega165/V 99 ...
Page 100
... The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x ATmega165/V DATA BUS (8-bit) OCRnxL Buf ...
Page 101
... Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. ATmega165/V 101 ...
Page 102
... The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “16-bit Timer/Counter Register Description” on page 113. The COM1x1:0 bits have no effect on the Input Capture unit. ATmega165 ...
Page 103
... The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. ATmega165/V 103 ...
Page 104
... OCnA The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. ATmega165 when OCR1A is set to zero (0x0000). The A ...
Page 105
... OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and com- pare values. ATmega165 TOP ...
Page 106
... This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The wave- form generated will have a maximum frequency of f zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the dou- ble buffer feature of the Output Compare unit is enabled in the fast PWM mode. ATmega165/V f clk_I/O = ---------------------------------- - ⋅ ...
Page 107
... PWM outputs. The small horizontal line marks on the TCNT1 slopes repre- sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 47. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 ATmega165 TOP log + 1 = ---------------------------------- - ...
Page 108
... BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1 the OC1A output will toggle with a 50% duty cycle. ATmega165/V f clk_I/O = --------------------------- - ⋅ ...
Page 109
... PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a com- pare match occurs. Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 2 ATmega165 TOP log + 1 = ---------------------------------- - ...
Page 110
... BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13 and COM1A1 the OC1A output will toggle with a 50% duty cycle. ATmega165/V f clk_I/O = --------------------------- - ⋅ ...
Page 111
... PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. ATmega165/V OCRnx OCRnx + 1 OCRnx Value ...
Page 112
... I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) ATmega165/V TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 ...
Page 113
... Table 49 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 49. Compare Output Mode, Fast PWM COM1A1/COM1B1 COM1A0/COM1B0 ATmega165 COM1B0 – – WGM11 WGM10 R R Description Normal port operation, OC1A/OC1B disconnected. Toggle OC1A/OC1B on Compare Match. ...
Page 114
... Table 51. Modes of operation sup- ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 103.). ATmega165/V Description Normal port operation, OC1A/OC1B disconnected. ...
Page 115
... ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag ATmega165/V Update of x TOP ...
Page 116
... FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. ATmega165 ...
Page 117
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 94. ATmega165 ...
Page 118
... Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts glob- ally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 46.) is executed when the TOV1 Flag, located in TIFR1, is set. ATmega165 ...
Page 119
... TOV1 Flag is set when the timer overflows. Refer to Table 51 on page 115 for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega165 ...
Page 120
... Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For the actual placement of I/O pins, refer to “Pinout ATmega165” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 121
... Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clk Timer/Counter clock. T2 ATmega165 default equal to the MCU clock, clk T2 TOVn (Int.Req.) clk Tn Control Logic Prescaler top ). T2 ...
Page 122
... Operation” on page 125). Figure 55 shows a block diagram of the Output Compare unit. Figure 55. Output Compare Unit, Block Diagram OCRnx top bottom FOCn ATmega165/V ). clk can be generated from an external or internal T2 is present or not. A CPU write overrides (has T2 DATA BUS TCNTn ...
Page 123
... Output Compare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2A1:0 bits are not double buffered together with the compare value. Changing the COM2A1:0 bits will take effect immediately. ATmega165/V 123 ...
Page 124
... PWM mode, refer to Table 56 on page 132, and for phase correct PWM refer to Table 57 on page 132. A change of the COM2A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2A strobe bits. ATmega165 OCnx ...
Page 125
... TOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the ATmega165/V OCnx Interrupt Flag Set (COMnx1 ...
Page 126
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 58. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period ATmega165/V f clk_I/O = ------------------------------------------------- - ⋅ ⋅ OCRnx ...
Page 127
... PWM mode is shown on Figure 59. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes repre- sent compare matches between OCR2A and TCNT2. ATmega165/V f clk_I/O f ...
Page 128
... OCR2A changes its value from MAX, like in Figure 59. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. ATmega165/V OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set ...
Page 129
... Figure 61 shows the same timing data, but with the prescaler enabled. Figure 61. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn Figure 62 shows the setting of OCF2A in all modes except CTC mode. ATmega165/V MAX BOTTOM BOTTOM + 1 /8) clk_I/O MAX BOTTOM BOTTOM + 1 should I/O 129 ...
Page 130
... Figure 63 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC) OCRnx OCFnx ATmega165/V OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM BOTTOM + 1 TOP /8) clk_I/O OCRnx + 2 130 ...
Page 131
... CTC Fast PWM Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def- initions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega165 COM2A0 WGM21 CS22 CS21 R/W R/W ...
Page 132
... A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See “Phase Cor- rect PWM Mode” on page 127 for more details. • Bit 2:0 – CS22:0: Clock Select ATmega165/V (1) (1) 132 ...
Page 133
... Initial Value The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2A pin. ATmega165/V Description No clock source (Timer/Counter stopped). clk /(No prescaling) T2S clk /8 (From prescaler) ...
Page 134
... The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When read- ing TCNT2, the actual timer value is read. When reading OCR2A or TCCR2A, the value in the temporary storage register is read. ATmega165 ...
Page 135
... Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power- down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. ATmega165/V 135 ...
Page 136
... When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. ATmega165/V ) again becomes active, TCNT2 will I/O 4 ...
Page 137
... Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. ATmega165 – ...
Page 138
... The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 90 for a description of the Timer/Counter Synchronization mode. ATmega165/V 10-BIT T/C PRESCALER Clear 0 ...
Page 139
... Serial Peripheral Interface – SPI 2573G–AVR–07/09 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega165 and peripheral devices or between several AVR devices. The ATmega165 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • ...
Page 140
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: Longer than 2 CPU clock cycles. High period. Longer tha 2 CPU clock cycles. ATmega165/V SHIFT ENABLE 140 ...
Page 141
... Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. ATmega165/V Direction, Slave SPI Input User Defined ...
Page 142
... DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; } Note: 1. See “About Code Examples” on page 6. ATmega165/V 142 ...
Page 143
... SPI_SlaveInit(void Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; } Note: 1. See “About Code Examples” on page 6. ATmega165/V 143 ...
Page 144
... When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. • Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. ATmega165 ...
Page 145
... SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f is shown in the following table: osc Table 62. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 ATmega165/V Leading Edge Trailing Edge Rising Falling Leading Edge Trailing Edge Sample Setup Sample SPR0 SCK Frequency osc osc f ...
Page 146
... WCOL set, and then accessing the SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATmega165 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 62) ...
Page 147
... SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB ATmega165/V Trailing eDge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...
Page 148
... Figure 69. USART Block Diagram UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA Note: 1. Refer to Figure 1 on page 2, Table 32 on page 66 for USART pin placement. ATmega165/V (1) Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL ...
Page 149
... U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 70 shows a block diagram of the clock generation logic. ATmega165/V 149 ...
Page 150
... However, the recovery units use a state machine that uses states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits. Table 64 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source. ATmega165 DDR_XCK ...
Page 151
... Receiver. This process introduces a two CPU clock period delay and therefore the max- imum external XCK clock frequency is limited by the following equation: Note that f depends on the stability of the system clock source therefore recom- osc mended to add some margin to avoid possible loss of data due to frequency variations. ATmega165/V Equation for Calculating (1) Baud Rate UBRR Value f ...
Page 152
... Figure 72 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. Figure 72. Frame Formats (IDLE Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. ATmega165/V Sample Sample FRAME 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 152 ...
Page 153
... TXC Flag can be used to check that the Transmitter has completed all transfers, and the RXC Flag can be used to check that there are no unread data in the receive buffer. Note that the TXC Flag must be cleared before each transmission (before UDR is written used for this purpose. ATmega165/V ⊕ … ⊕ ...
Page 154
... More advanced initialization routines can be made that include frame format as parame- ters, disable interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules. ATmega165/V 154 ...
Page 155
... See “About Code Examples” on page 6. The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before loading it with new data to be transmitted. If the Data Register Empty inter- rupt is utilized, the interrupt routine writes the data into the buffer. ATmega165/V 155 ...
Page 156
... UCSRB is static. For example, only the TXB8 bit of the UCSRB Register is used after initialization. 2. See “About Code Examples” on page 6. The ninth bit can be used for indicating an address frame when using multi processor communication mode or for other protocol handling as for example synchronization. ATmega165/V 156 ...
Page 157
... The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When dis- abled, the Transmitter will no longer override the TxD pin. ATmega165/V 157 ...
Page 158
... Get and return received data from buffer */ return UDR; } Note: 1. See “About Code Examples” on page 6. The function simply waits for data to be present in the receive buffer by checking the RXC Flag, before reading the buffer and returning the value. ATmega165/V 158 ...
Page 159
... UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<UPE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); } Note: 1. See “About Code Examples” on page 6. ATmega165/V 159 ...
Page 160
... Error when received. If Parity Check is not enabled the UPE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 153 and “Parity Checker” on page 161. ATmega165/V 160 ...
Page 161
... The data recovery logic samples and low pass filters each incoming bit, thereby improv- ing the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. ATmega165/V 161 ...
Page 162
... This majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. ATmega165/V START 5 6 ...
Page 163
... Table 65 and Table 66 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. ATmega165/V STOP 1 (A) (B) 5 ...
Page 164
... The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low error can be used if possible. ATmega165/V Recommended Max (%) Max Total Error (%) ...
Page 165
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. ATmega165/V 165 ...
Page 166
... The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed can be cleared by writing a one to its bit location. The TXC Flag can generate a Transmit Complete interrupt (see description of the TXCIE bit). ATmega165 ...
Page 167
... This bit enables the Multi-processor Communication mode. When the MPCM bit is writ- ten to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 165. ATmega165/V 167 ...
Page 168
... Must be read before reading the low bits from UDR. • Bit 0 – TXB8: Transmit Data Bit 8 TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR. ATmega165 ...
Page 169
... UPM1 UPM0 • Bit 3 – USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 69. USBS Bit Settings USBS 0 1 ATmega165 UPM0 USBS UCSZ1 UCSZ0 R/W R/W R/W R Parity Mode ...
Page 170
... UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor- rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. ATmega165/V UCSZ0 Character Size 0 ...
Page 171
... ATmega165/V BaudRate ⎛ ⎞ Closest Match • ------------------------------------------------------- - 1 100% – ⎝ ⎠ BaudRate f = 2.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0. ...
Page 172
... Mbps ATmega165 7.3728 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0. ...
Page 173
... Mbps 691.2 kbps ATmega165/V MHz f = 14.7456 MHz osc U2X = 1 U2X = 0 Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0. ...
Page 174
... Mbps 1.152 Mbps ATmega165 20.0000 MHz osc U2X = 1 U2X = 0 Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0. ...
Page 175
... Two-wire Start Condition Detector with Interrupt Capability A simplified block diagram of the USI is shown on Figure 76. For the actual placement of I/O pins, refer to “Pinout ATmega165” on page 2. CPU accessible I/O Registers, includ- ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “ ...
Page 176
... The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. Figure 78. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 USCK USCK DO MSB 6 DI MSB ATmega165 Bit0 USCK DO DI Bit0 USCK PORTxn ...
Page 177
... The second and third instructions clears the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. ATmega165/V 177 ...
Page 178
... DO is configured as output and USCK pin is configured as input in the DDR Register. The value stored in register r16 prior to the function is called is trans- ferred to the master device, and when the transfer is completed the data received from the Master is stored back into the r16 Register. ATmega165/V 178 ...
Page 179
... The clock is generated by the master by toggling the USCK pin via the PORT Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. ATmega165/V SDA Bit1 Bit0 ...
Page 180
... If the Slave is not able to receive more data it does not acknowledge the data byte it has last received. When the Master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted. Figure 81. Start Condition Detector, Logic Diagram SDA SCL Write( USISIF) ATmega165 ACK DATA ...
Page 181
... Shift Register. The output pin in use SDA depending on the wire mode, is connected via the out- put latch to the most significant bit (bit 7) of the Data Register. The output latch is open ATmega165/V /4. This is also the maximum data transmit CK ...
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... Bits 3..0 – USICNT3..0: Counter Value These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. The 4-bit counter increments by one for each clock generated either by the external clock edge detector Timer/Counter0 Compare Match software using USI- ATmega165 ...
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... Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and Shift Register can therefore be clocked externally, and data input sampled, even when outputs are dis- abled. The relations between USIWM1..0 and the USI operation is summarized in Table 76. ATmega165 ...
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... SCL line is also held low when a counter overflow occurs, and is held low until the Counter Overflow Flag (USIOIF) is cleared. Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion between the modes of operation. ATmega165/V (1) . 184 ...
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... When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. ATmega165/V 4-bit Counter Clock Source ...
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... N/A • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power ATmega165/V (2) ACIE INTERRUPT SELECT ACIS1 ACIS0 ...
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... Comparator Interrupt on Falling Output Edge Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis- abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. ATmega165/V 187 ...
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... The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ATmega165/V Analog Comparator Negative Input AIN1 AIN1 ...
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... Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The ATmega165 features a 10-bit successive approximation ADC. The ADC is con- nected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND) ...
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... If the result is left adjusted and no more than 8-bit precision is required sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access ATmega165/V ADC CONVERSION COMPLETE IRQ ...
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... ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. ATmega165/V PRESCALER START ADATE CONVERSION ...
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... ADC must be disabled and re-enabled after every conversion. In Free Running mode, a new conversion will be started immediately after the conver- sion completes, while ADSC remains high. For a summary of conversion times, see Table 80. ATmega165/V Reset 7-BIT ADC PRESCALER ADC CLOCK SOURCE ...
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... Sample & Hold MUX and REFS Update Figure 88. ADC Timing Diagram, Auto Triggered Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL Sample & Prescaler Hold Reset MUX and REFS Update ATmega165/V First Conversion Conversion Sample & Hold Complete One Conversion ...
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... Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete Table 80. ADC Conversion Time Condition First conversion Normal conversions, single ended Auto Triggered conversions ATmega165/V Next Conversion Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Sample & Hold (Cycles ...
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... If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage external voltage is applied to the AREF pin, the user may switch ATmega165/V ) indicates the conversion range for the ADC. REF will result in codes close to 0x3FF ...
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... The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 90. Analog Input Circuitry I IH ADCn ATmega165/V /2) should not be present for ADC 1..100 kΩ S/H ...
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... ADC noise canceler function to reduce induced noise from the CPU. 4.If any ADC port pins are used as digital outputs essential that these do not switch while a conversion is in progress. Figure 91. ADC Power Connections 100nF Analog Ground Plane ATmega165/V CC PA0 51 VCC 52 ...
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... Figure 93. Gain Error Output Code • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. ATmega165 REF n -1. Ideal ADC Actual ADC ...
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... Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB. ATmega165/V Ideal ADC Actual ADC V Input Voltage ...
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... IN ence (see Table 82 on page 201 and Table 83 on page 202). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. ADC Figure 96. Differential Measurement Range Output Code - V 0x3FF REF ATmega165/V ⋅ V 1024 IN = -------------------------- V REF the selected voltage refer- ...