ATMEGA165-16AI Atmel, ATMEGA165-16AI Datasheet - Page 242

• Manufacturer Part Number: ATMEGA165-16AI
• Description: IC AVR MCU 16K 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Preventing Flash Corruption
Programming Time for Flash
when Using SPM
2573G–AVR–07/09
the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destina-
tion register as shown below. Refer to Table 101 on page 247 for detailed description
and mapping of the Extended Fuse byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that
are unprogrammed, will be read as one.
During periods of low V
age is too low for the CPU and the Flash to operate properly. These issues are the same
as for board level systems using the Flash, and the same design solutions should be
applied.
A Flash program corruption can be caused by two situations when the voltage is too low.
First, a regular write sequence to the Flash requires a minimum voltage to operate cor-
rectly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage
for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one
is sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot
2. Keep the AVR RESET active (low) during periods of insufficient power supply
3. Keep the AVR core in Power-down sleep mode during periods of low V
The calibrated RC Oscillator is used to time Flash accesses. Table 95 shows the typical
programming time for Flash accesses from the CPU.
Table 95. SPM Programming Time
Bit
Rd
Flash write (Page Erase, Page Write,
and write Lock bits by SPM)
Loader Lock bits to prevent any Boot Loader software updates.
voltage. This can be done by enabling the internal Brown-out Detector (BOD) if
the operating voltage matches the detection level. If not, an external low V
reset protection circuit can be used. If a reset occurs while a write operation is in
progress, the write operation will be completed provided that the power supply
voltage is sufficient.
will prevent the CPU from attempting to decode and execute instructions, effec-
tively protecting the SPMCSR Register and thus the Flash from unintentional
writes.
Symbol
7
–
CC
6
–
, the Flash program can be corrupted because the supply volt-
5
–
Min Programming Time
4
–
3.7 ms
EFB3
3
EFB2
2
ATmega165/V
Max Programming Time
EFB1
1
4.5 ms
EFB0
0
CC
. This
CC
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