PIC18C242/JW Microchip Technology, PIC18C242/JW Datasheet - Page 229
![IC MCU EPROM 8KX16 A/D 28CDIP](/photos/7/29/72984/150-28-cdip_sml.jpg)
PIC18C242/JW
Manufacturer Part Number
PIC18C242/JW
Description
IC MCU EPROM 8KX16 A/D 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C242/JW
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
EPROM, UV
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C242/JW
Manufacturer:
NS
Quantity:
10
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 229 of 305
- Download datasheet (6Mb)
TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
2001 Microchip Technology Inc.
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC = Address(HERE)
If CNT
If CNT
Q1
Q1
Q1
PC
PC
register ’f’
operation
operation
operation
Test f, skip if 0
[ label ] TSTFSZ f [,a]
0
a
skip if f = 0
None
If ’f’ = 0, the next instruction,
fetched during the current instruc-
tion execution, is discarded and a
NOP is executed, making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
No
No
No
Q2
Q2
Q2
=
=
=
f
[0,1]
by a 2-word instruction.
255
0x00,
Address (ZERO)
0x00,
Address (NZERO)
:
TSTFSZ
011a
:
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
CNT, 1
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WREG
WREG
Q1
=
=
literal ’k’
Exclusive OR literal with WREG
[ label ] XORLW k
0
(WREG) .XOR. k
N,Z
The contents of WREG are
XORed with the 8-bit literal 'k'.
The result is placed in WREG.
1
1
XORLW 0xAF
Read
Q2
0000
0xB5
0x1A
k
PIC18CXX2
255
1010
Process
Data
Q3
DS39026C-page 227
kkkk
WREG
Write to
WREG
Q4
kkkk
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