PIC18C242/JW Microchip Technology, PIC18C242/JW Datasheet - Page 144

• Manufacturer Part Number: PIC18C242/JW
• Description: IC MCU EPROM 8KX16 A/D 28CDIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242/JW

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: EPROM, UV
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-CDIP (0.300", 7.62mm) Window
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PIC18CXX2
14.4.10
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
is presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (T
SCL pin is de-asserted (pulled high). When the SCL pin
is sampled high (clock arbitration), the baud rate gener-
ator counts for T
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 14-20).
14.4.10.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 14-20:
DS39026C-page 142
ACKNOWLEDGE SEQUENCE
TIMING
Note: T
WCOL Status Flag
BRG
sequence
SSPIF
Acknowledge sequence starts here,
SDA
BRG
. The SCL pin is then pulled low. Fol-
SCL
ACKNOWLEDGE SEQUENCE WAVEFORM
= one baud rate generator period.
Set SSPIF at the end
of receive
ACKEN = 1, ACKDT = 0
enable
Write to SSPCON2
bit,
BRG
8
D0
) and the
ACKEN
Cleared in
software
T
BRG
ACK
14.4.11
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the STOP sequence enable
bit, PEN (SSPCON2<2>). At the end of a receive/trans-
mit, the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low. When the SDA line is sampled
low, the baud rate generator is reloaded and counts
down to 0. When the baud rate generator times out, the
SCL pin will be brought high, and one T
generator rollover count) later, the SDA pin will be
de-asserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A T
later, the PEN bit is cleared and the SSPIF bit is set
(Figure 14-21).
14.4.11.1
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
T
BRG
9
Set SSPIF at the end
of Acknowledge sequence
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
Cleared in
software
2001 Microchip Technology Inc.
BRG
(baud rate
BRG