UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 77
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 77 of 889
- Download datasheet (11Mb)
V850ES/JG3
3.4.8
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) Registers to be set first
Be sure to set the following registers first when using the V850ES/JG3.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM)
• Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related
registers after setting the above registers.
(a) System wait control register (VSWC)
(b) On-chip debug mode register (OCDM)
(c) Watchdog timer mode register 2 (WDTM2)
Cautions
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.
Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The V850ES/JG3
requires wait cycles according to the operating frequency. Set the following value to the VSWC register in
accordance with the frequency used.
The VSWC register can be read or written in 8-bit units (address: FFFFF06EH, default value: 77H).
For details, see CHAPTER 28 ON-CHIP DEBUG FUNCTION.
The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.
Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register to
activate this operation.
For details, refer to CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2.
32 kHz ≤ f
16.6 MHz ≤ f
25 MHz ≤ f
Operating Frequency (f
CLK
CLK
CLK
< 16.6 MHz
≤ 32 MHz
< 25 MHz
CLK
)
Set Value of VSWC
00H
01H
11H
Number of Waits
0 (no waits)
CHAPTER 3 CPU FUNCTION
1
2
Page 61 of 870
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