UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 184
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (11Mb)
V850ES/JG3
5.9
executed in the external bus cycle.
instruction fetch (successive).
accesses due to bus size limitations.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are
Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and
An instruction fetch may be inserted between the read access and write access in a read-modify-write access.
If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between
Bus Priority
Priority
High
Low
Bus hold
DMA transfer
Operand data access
Instruction fetch (branch)
Instruction fetch (successive)
Table 5-4. Bus Priority
External Bus Cycle
CHAPTER 5 BUS CONTROL FUNCTION
External device
DMAC
CPU
CPU
CPU
Bus Master
Page 168 of 870
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