UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 269
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 269 of 889
- Download datasheet (11Mb)
V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
TPnCTL0
TPnCTL1
TPnIOC0
(a) TMPn control register 0 (TPnCTL0)
(b) TMPn control register 1 (TPnCTL1)
(c) TMPn I/O control register 0 (TPnIOC0)
Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1
TPnCE
0/1
0
0
TPnEST
0
0
0
Figure 7-31. Register Setting in Free-Running Timer Mode (1/2)
TPnEEE
0/1
0
0
0
0
0
TPnOL1
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
0/1
0
0
TPnCKS2 TPnCKS1 TPnCKS0
TPnOE1 TPnOL0
TPnMD2 TPnMD1 TPnMD0
0/1
0/1
1
0/1
0/1
0
TPnOE0
0/1
0/1
1
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level with
operation of TOPn0 pin disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Setting of output level with
operation of TOPn1 pin disabled
0: Low level
1: High level
1, 0, 1:
Free-running mode
Select count clock
0: Stop counting
1: Enable counting
0: Operate with count
1: Count on external
clock selected by
TPnCKS0 to TPnCKS2 bits
event count input signal
Note
Page 253 of 870
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