UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 178
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3
5.6.2
inserted in the bus cycle by using the external wait pin (WAIT).
external wait function, in the same manner as the programmable wait function.
TW states of the bus cycle in the multiplexed bus mode. In the separate bus mode, it is sampled at the rising edge of the
clock immediately after the T1 and TW states of the bus cycle. If the setup/hold time of the sampling timing is not satisfied,
a wait state is inserted in the next state, or not inserted at all.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be
When the PCM0 pin is set to alternate function, the external wait function is enabled.
Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the
The WAIT signal can be input asynchronously to CLKOUT, and is sampled at the falling edge of the clock in the T2 and
External wait function
CHAPTER 5 BUS CONTROL FUNCTION
Page 162 of 870
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