UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 221
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3
the count clock, and the counter starts counting. At this time, the output of the TOPn0 pin is inverted. Additionally, the set
value of the TPnCCR0 register is transferred to the CCR0 buffer register.
to 0000H, the output of the TOPn0 pin is inverted, and a compare match interrupt request signal (INTTPnCC0) is
generated.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
TPnCTL0
TPnCTL1
When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
The interval can be calculated by the following expression.
Interval = (Set value of TPnCCR0 register + 1) × Count clock cycle
Remark
Note This bit can be set to 1 only when the interrupt request signals (INTTPnCC0 and INTTPnCC1) are masked
(a) TMPn control register 0 (TPnCTL0)
(b) TMPn control register 1 (TPnCTL1)
by the interrupt mask flags (TPnCCMK0 and TPnCCMK1) and timer output (TOPn1) is performed at the
same time. However, set the TPnCCR0 and TPnCCR1 registers to the same value (see 7.5.1 (2) (d)
Operation of TPnCCR1 register).
TPnCE
n = 0 to 5
0/1
0
TPnEST
0
0
Figure 7-4. Register Setting for Interval Timer Mode Operation (1/2)
TPnEEE
0/1
0
Note
0
0
0
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TPnCKS2 TPnCKS1 TPnCKS0
TPnMD2 TPnMD1 TPnMD0
0/1
0
0/1
0
0/1
0
Select count clock
0: Stop counting
1: Enable counting
0, 0, 0:
Interval timer mode
0: Operate on count
1: Count with external
clock selected by
TPnCKS0 to TPnCKS2 bits
event count input signal
Page 205 of 870
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