UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 241
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 241 of 889
- Download datasheet (11Mb)
V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
TPnIOC2
(d) TMPn I/O control register 2 (TPnIOC2)
(e) TMPn counter read buffer register (TPnCNT)
(f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
The value of the 16-bit counter can be read by reading the TPnCNT register.
If D
waveform are as follows.
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not used
Cycle = (D
Active level width = D
Figure 7-18. Register Setting for Operation in External Trigger Pulse Output Mode (2/2)
0
0
is set to the TPnCCR0 register and D
2. n = 0 to 5
0
+ 1) × Count clock cycle
in the external trigger pulse output mode.
0
1
0
× Count clock cycle
0
TPnEES1
1
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
to the TPnCCR1 register, the cycle and active level of the PWM
TPnEES0 TPnETS1 TPnETS0
0
0/1
0/1
Select valid edge of
external trigger input
Page 225 of 870
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