UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 664
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (11Mb)
V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Interrupt request a
Interrupt request c
Interrupt request e
Interrupt request g
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
Remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of
Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued
(level 3)
(level 3)
(level 2)
(level 1)
2. The default priority in the figure indicates the relative priority between two interrupt request
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
explanation.
signals.
Main routine
EI
Interrupt request f
Interrupt request d
Interrupt request h
Interrupt
request b
(level 2)
(level 1)
(level 3)
(level 2)
While an Interrupt Is Being Serviced (1/2)
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
EI
EI
EI
Servicing of a
Servicing of c
Servicing of d
Servicing of e
Servicing of f
Servicing of g
Servicing of h
Servicing of b
Interrupt request b is acknowledged because the
priority of b is higher than that of a and interrupts are
enabled.
Although the priority of interrupt request d is higher
than that of c, d is held pending because interrupts
are disabled.
Interrupt request f is held pending even if interrupts are
enabled because its priority is lower than that of e.
Interrupt request h is held pending even if interrupts are
enabled because its priority is the same as that of g.
Page 648 of 870
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