UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 226
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 226 of 889
- Download datasheet (11Mb)
V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(c) Notes on rewriting TPnCCR0 register
To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
Remarks 1. Interval time (1): (D
If the value of the TPnCCR0 register is changed from D
than D
rewritten. Consequently, the value of the 16-bit counter that is compared is D
Because the count value has already exceeded D
and then counts up again from 0000H. When the count value matches D
and the output of the TOPn0 pin is inverted.
Therefore, the INTTPnCC0 signal may not be generated at the interval time “(D
“(D
Count clock period”.
2
+ 1) × Count clock cycle” originally expected, but may be generated at an interval of “(10000H + D
INTTPnCC0 signal
1
TPnCCR0 register
, the count value is transferred to the CCR0 buffer register as soon as the TPnCCR0 register has been
TOPn0 pin output
16-bit counter
2. n = 0 to 5
TPnOL0 bit
Interval time (NG): (10000H + D
Interval time (2): (D
TPnCE bit
FFFFH
0000H
L
Interval time (1)
1
2
+ 1) × Count clock cycle
+ 1) × Count clock cycle
D
1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
D
1
2
+ 1) × Count clock cycle
2
, however, the 16-bit counter counts up to FFFFH, overflows,
D
2
Interval time (NG)
D
1
1
to D
2
while the count value is greater than D
D
2
D
2
2
, the INTTPnCC0 signal is generated
Interval
time (2)
2
D
.
2
1
+ 1) × Count clock cycle” or
Page 210 of 870
2
but less
2
+ 1) ×
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