HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 79

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4.6
In some cases, address errors and interrupts that directly follow a delayed branch instruction or
interrupt-disabled instruction are not accepted immediately. Table 4.9 lists these cases. When this
occurs, the exception is accepted when an instruction that can accept the exception is decoded.
Table 4.9
Immediately after delayed branch instruction*
Immediately after interrupt-disabled instruction*
X: Not accepted
O: Accepted
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE
4.6.1
Address errors and interrupts are not accepted when an instruction in a delay slot immediately
following a delayed branch instruction is decoded. The delayed branch instruction and the
instruction in the delay slot are therefore always executed one after the other. Exception
processing is never inserted between them.
4.6.2
Interrupts are not accepted when the instruction immediately following an interrupt-disabled
instruction is decoded. Address errors are accepted, however.
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
Cases in Which Exceptions Are Not Accepted
Immediately after Delayed Branch Instructions
Immediately after Interrupt-Disabling Instructions
Cases in Which Exceptions Are Not Accepted
Case
1
2
Address Error
X
O
Exception Source
Interrupt
X
X
RENESAS 57

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