HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 265

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Free-running count and periodic count
A reset of the counters for channels 0–4 leaves them all in the free-running mode. When a
corresponding bit in the TSTR is set to 1, the corresponding timer counter operates as a free-
running counter and begins to increment. When the count wraps around from H'FFFF–H'0000,
the overflow flag (OVF) in the timer status register (TSR) is set to 1. If the OVIE bit in the
timer’s corresponding interrupt enable register (TIER) is set to 1, the CPU will be asked for an
interrupt. After the TCNT overflows, counting continues from H'0000. Figure 10.15 shows an
example of free-running counting.
Periodic counter operation is obtained for a given channel’s TCNT by selecting compare match
as a TCNT clear source. (Set the GRA or GRB for period setting to output compare register
and select counter clear upon compare match using the CCLR1 and CCLR0 bits of the timer
control register (TCR).) After setting, the TCNT begins incrementing as a periodic counter
when the corresponding bit of TSTR is set to 1. When the count matches GRA or GRB, the
IMFA/IMFB bit in the TSR is set to 1 and the counter is automatically cleared to H'0000. If the
IMIEA/IMIEB bit of the corresponding TIER is set to 1 at this point, the CPU will be asked for
an interrupt. After the compare match, TCNT continues counting from H'0000. Figure 10.16
shows an example of periodic counting.
TCNT value
H'FFFF
H'0000
Time
STR0–STR4
OVF
Figure 10.15 Free-Running Counter Operation
RENESAS 247

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