HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 334

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Bit 0: G0NOV
0
1
11.3
11.3.1
When corresponding bits in the PBCR1, PBCR2, NDERA and NDERB registers are set to 1, TPC
output is enabled and the PBDR data register values are output. After that, when the compare-
match event selected by TPCR occurs, the next data register contents (NDRA and NDRB) are
transferred to the PBDR and output values are updated. Figure 11.2 illustrates the TPC output
operation.
If new data is written in next data registers A and B before the next compare-match occurs, a
maximum 16 bits of data can be output at each successive compare-match. See section 11.3.4,
TPC Output Non-Overlap Operation, for details on non-overlap operation.
316 RENESAS
output pin
TPC
Operation
Overview
Port function
select
CR
Q
Description
TPC output group 0 operates normally (output value updated according
to compare-match A of the ITU channel selected by TPCR) (initial
value)
TPC output group 0 operates in non-overlap mode (1 output and 0
output can be performed independently according to compare-match A
and B of the ITU channel selected by TPCR)
Figure 11.2 TPC Output Operation
Q
NDER
Q
DR
C
Output trigger
signal
D
Q
NDR
D
Internal
data bus