HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 222

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
detection and DACK active low) (Single address mode, bus cycle = Address/data multiplex
detection and DACK active low) (Dual address mode, bus cycle = Address/data multiplex
Note:
Figure 9.21 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
Figure 9.22 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
Bus cycle
Bus cycle
DREQ
DACK
DREQ
DACK
When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer
will be executed because the sampling is done at the second state of the DMAC cycle.
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA
transfer will be executed because the sampling is done at the second state of the
DMAC cycle.
CK
CK
CPU
CPU
CPU
CPU
CPU
CPU
T1
DMAC(R)
I/O bus cycle)
I/O bus cycle)
T2
T1
T3
T2
DMAC
T4
T3
DMAC
(W)
T4
CPU
CPU
DMAC (W): DMAC write cycle
DMAC (R): DMAC read cycle
T1
DMAC (R)
T1
T2
T3
T2
DMAC
T4
T3
DMAC
T4
(W)
RENESAS 203
CPU
CPU

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