HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 25

MCU 5V 32K PB-FREE 100-TQFP

HD6477021X20V

Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6477021X20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 1.1
Feature
CPU
Operating modes
2 RENESAS
Features of the SH7020 and SH7021 Microcomputers
Description
Original Hitachi architecture
32-bit internal data paths
General-register machine:
• Sixteen 32-bit general registers
• Three 32-bit control registers
• Four 32-bit system registers
RISC-type instruction set:
• Instruction length: 16-bit fixed length for improved code
• Load-store architecture (basic arithmetic and logic operations
• Delayed unconditional branch instructions reduce pipeline
• Instruction set optimized for C language
Instruction execution time: one instruction/cycle (50 ns/instruction
at 20-MHz operation)
Address space: 4 Gbytes available on the architecture
On-chip multiplier: multiplication operations (16 bits
32 bits) executed in 1–3 cycles, and multiplication/accumulation
operations (16 bits
cycles
Five-stage pipeline
Operating modes:
• On-chip ROMless mode
• On-chip ROM mode
Processing states:
• Power-on reset state
• Manual reset state
• Exception processing state
• Program execution state
• Power-down state
• Bus-released state
Power-down states:
• Sleep mode
• Software standby mode
efficiency
are executed between registers)
disruption
16 bits + 42 bits
42 bits) executed in 2–3
16 bits

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